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translate-a64: Backport fix for incorrect load/store exclusive unallocated checks

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Backports commit e14f0eb12f920fd96b9f79d15cedd437648e8667 from qemu
This commit is contained in:
Lioncash 2018-02-04 23:17:28 -05:00
parent c25f059530
commit 1e451b386a
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 13 deletions
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15
qemu/target-arm/translate-a64.c
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@ -1783,9 +1783,6 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
* o2: 0 -> exclusive, 1 -> not
* o1: 0 -> single register, 1 -> register pair
* o0: 1 -> load-acquire/store-release, 0 -> not
*
* o0 == 0 AND o2 == 1 is un-allocated
* o1 == 1 is un-allocated except for 32 and 64 bit sizes
*/
static void disas_ldst_excl(DisasContext *s, uint32_t insn)
{
@ -1801,7 +1798,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
int size = extract32(insn, 30, 2);
TCGv_i64 tcg_addr;
if ((!is_excl && !is_lasr) ||
if ((!is_excl && !is_pair && !is_lasr) ||
(!is_excl && is_pair) ||
(is_pair && size < 2)) {
unallocated_encoding(s);
return;
@ -1830,15 +1828,6 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
} else {
do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false);
}
if (is_pair) {
TCGv_i64 tcg_rt2 = cpu_reg(s, rt);
tcg_gen_addi_i64(tcg_ctx, tcg_addr, tcg_addr, 1ULL << size);
if (is_store) {
do_gpr_st(s, tcg_rt2, tcg_addr, size);
} else {
do_gpr_ld(s, tcg_rt2, tcg_addr, size, false, false);
}
}
}
}