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tcg/i386: Tidy register constraint definitions

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Create symbolic constants for all low-byte-addressable
and second-byte-addressable registers. Create a symbol
for the registers that need reserving for softmmu.

There is no functional change for 's', as this letter is
only used for i386. The BYTEL name is correct for the
action we wish from the constraint.

Backports df903b94b3c6fa515da7cf2103513ade06ab0d0f
This commit is contained in:
Richard Henderson 2021-03-04 15:48:10 -05:00 committed by Lioncash
parent ea25434061
commit 1e8da15e61
1 changed files with 20 additions and 20 deletions
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40
qemu/tcg/i386/tcg-target.inc.c
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@ -138,6 +138,22 @@ static const int tcg_target_call_oarg_regs[] = {
# define TCG_REG_L1 TCG_REG_EDX # define TCG_REG_L1 TCG_REG_EDX
#endif #endif
#define ALL_BYTEH_REGS 0x0000000fu
#if TCG_TARGET_REG_BITS == 64
# define ALL_GENERAL_REGS 0x0000ffffu
# define ALL_VECTOR_REGS 0xffff0000u
# define ALL_BYTEL_REGS ALL_GENERAL_REGS
#else
# define ALL_GENERAL_REGS 0x000000ffu
# define ALL_VECTOR_REGS 0x00ff0000u
# define ALL_BYTEL_REGS ALL_BYTEH_REGS
#endif
#ifdef CONFIG_SOFTMMU
# define SOFTMMU_RESERVE_REGS ((1 << TCG_REG_L0) | (1 << TCG_REG_L1))
#else
# define SOFTMMU_RESERVE_REGS 0
#endif
/* The host compiler should supply <cpuid.h> to enable runtime features /* The host compiler should supply <cpuid.h> to enable runtime features
detection, as we're not going to go so far as our own inline assembly. detection, as we're not going to go so far as our own inline assembly.
If not available, default values will be assumed. */ If not available, default values will be assumed. */
@ -200,14 +216,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
return true; return true;
} }
#if TCG_TARGET_REG_BITS == 64
#define ALL_GENERAL_REGS 0x0000ffffu
#define ALL_VECTOR_REGS 0xffff0000u
#else
#define ALL_GENERAL_REGS 0x000000ffu
#define ALL_VECTOR_REGS 0x00ff0000u
#endif
/* parse target specific constraints */ /* parse target specific constraints */
static const char *target_parse_constraint(TCGArgConstraint *ct, static const char *target_parse_constraint(TCGArgConstraint *ct,
const char *ct_str, TCGType type) const char *ct_str, TCGType type)
@ -233,11 +241,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
break; break;
case 'q': case 'q':
/* A register that can be used as a byte operand. */ /* A register that can be used as a byte operand. */
ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf; ct->regs |= ALL_BYTEL_REGS;
break; break;
case 'Q': case 'Q':
/* A register with an addressable second byte (e.g. %ah). */ /* A register with an addressable second byte (e.g. %ah). */
ct->regs = 0xf; ct->regs |= ALL_BYTEH_REGS;
break; break;
case 'r': case 'r':
/* A general register. */ /* A general register. */
@ -254,19 +262,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
case 'L': case 'L':
/* qemu_ld/st data+address constraint */ /* qemu_ld/st data+address constraint */
ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; ct->regs |= ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS;
#ifdef CONFIG_SOFTMMU
tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
#endif
break; break;
case 's': case 's':
/* qemu_st8_i32 data constraint */ /* qemu_st8_i32 data constraint */
ct->regs = 0xf; ct->regs |= ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS;
#ifdef CONFIG_SOFTMMU
tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
#endif
break; break;
case 'e': case 'e':