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target/arm: Introduce raise_exception_ra

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This path uses cpu_loop_exit_restore to unwind current processor state.

Backports commit 7469f6c696d74ad3b22b67c08e1e8f79e2b5d3d6 from qemu
This commit is contained in:
Richard Henderson 2019-01-22 15:18:47 -05:00 committed by Lioncash
parent e6ffbc22c2
commit 1f7d228c8a
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GPG key ID: 4E3C3CC1031BA9C7
7 changed files with 30 additions and 2 deletions
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1
qemu/aarch64.h
View file

@ -4268,6 +4268,7 @@
#define new_tmp_a64_zero new_tmp_a64_zero_aarch64
#define pred_esz_masks pred_esz_masks_aarch64
#define raise_exception raise_exception_aarch64
#define raise_exception_ra raise_exception_ra_aarch64
#define read_cpu_reg read_cpu_reg_aarch64
#define read_cpu_reg_sp read_cpu_reg_sp_aarch64
#define sli_op sli_op_aarch64

1
qemu/aarch64eb.h
View file

@ -4268,6 +4268,7 @@
#define new_tmp_a64_zero new_tmp_a64_zero_aarch64eb
#define pred_esz_masks pred_esz_masks_aarch64eb
#define raise_exception raise_exception_aarch64eb
#define raise_exception_ra raise_exception_ra_aarch64eb
#define read_cpu_reg read_cpu_reg_aarch64eb
#define read_cpu_reg_sp read_cpu_reg_sp_aarch64eb
#define sli_op sli_op_aarch64eb

1
qemu/arm.h
View file

@ -3286,6 +3286,7 @@
#define mla_op mla_op_arm
#define mls_op mls_op_arm
#define raise_exception raise_exception_arm
#define raise_exception_ra raise_exception_ra_arm
#define sli_op sli_op_arm
#define ssra_op ssra_op_arm
#define sri_op sri_op_arm

1
qemu/armeb.h
View file

@ -3286,6 +3286,7 @@
#define mla_op mla_op_armeb
#define mls_op mls_op_armeb
#define raise_exception raise_exception_armeb
#define raise_exception_ra raise_exception_ra_armeb
#define sli_op sli_op_armeb
#define ssra_op ssra_op_armeb
#define sri_op sri_op_armeb

2
qemu/header_gen.py
View file

@ -3295,6 +3295,7 @@ arm_symbols = (
'mla_op',
'mls_op',
'raise_exception',
'raise_exception_ra',
'sli_op',
'ssra_op',
'sri_op',
@ -4302,6 +4303,7 @@ aarch64_symbols = (
'new_tmp_a64_zero',
'pred_esz_masks',
'raise_exception',
'raise_exception_ra',
'read_cpu_reg',
'read_cpu_reg_sp',
'sli_op',

7
qemu/target/arm/internals.h
View file

@ -103,6 +103,13 @@ FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
void QEMU_NORETURN raise_exception(CPUARMState *env, uint32_t excp,
uint32_t syndrome, uint32_t target_el);
/*
* Similarly, but also use unwinding to restore cpu state.
*/
void QEMU_NORETURN raise_exception_ra(CPUARMState *env, uint32_t excp,
uint32_t syndrome, uint32_t target_el,
uintptr_t ra);
/*
* For AArch64, map a given EL to an index in the banked_spsr array.
* Note that this mapping and the AArch32 mapping defined in bank_number()

19
qemu/target/arm/op_helper.c
View file

@ -27,8 +27,8 @@
#define SIGNBIT (uint32_t)0x80000000
#define SIGNBIT64 ((uint64_t)1 << 63)
void raise_exception(CPUARMState *env, uint32_t excp,
uint32_t syndrome, uint32_t target_el)
static CPUState *do_raise_exception(CPUARMState *env, uint32_t excp,
uint32_t syndrome, uint32_t target_el)
{
CPUState *cs = CPU(arm_env_get_cpu(env));
@ -49,9 +49,24 @@ void raise_exception(CPUARMState *env, uint32_t excp,
cs->exception_index = excp;
env->exception.syndrome = syndrome;
env->exception.target_el = target_el;
return cs;
}
void raise_exception(CPUARMState *env, uint32_t excp,
uint32_t syndrome, uint32_t target_el)
{
CPUState *cs = do_raise_exception(env, excp, syndrome, target_el);
cpu_loop_exit(cs);
}
void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
uint32_t target_el, uintptr_t ra)
{
CPUState *cs = do_raise_exception(env, excp, syndrome, target_el);
cpu_loop_exit_restore(cs, ra);
}
static int exception_target_el(CPUARMState *env)
{
int target_el = MAX(1, arm_current_el(env));