mirror of
https://github.com/yuzu-emu/unicorn.git
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tcg: Move some opcode generation functions out of line
Backports commit 951c6300f74ace35d87c079affc57cfc513a6a35 from qemu
This commit is contained in:
Lioncash
parent
cb7b19ad26
commit
203b2107d6
2011
qemu/tcg/tcg-op.c
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2011
qemu/tcg/tcg-op.c
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2432
qemu/tcg/tcg-op.h
2432
qemu/tcg/tcg-op.h
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170
qemu/tcg/tcg.c
170
qemu/tcg/tcg.c
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@ -853,176 +853,6 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
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#endif /* TCG_TARGET_EXTEND_ARGS */
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#endif /* TCG_TARGET_EXTEND_ARGS */
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}
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}
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#if TCG_TARGET_REG_BITS == 32
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void tcg_gen_shifti_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1,
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int c, int right, int arith)
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{
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if (c == 0) {
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tcg_gen_mov_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1));
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tcg_gen_mov_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1));
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} else if (c >= 32) {
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c -= 32;
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if (right) {
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if (arith) {
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tcg_gen_sari_i32(s, TCGV_LOW(ret), TCGV_HIGH(arg1), c);
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tcg_gen_sari_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), 31);
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} else {
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tcg_gen_shri_i32(s, TCGV_LOW(ret), TCGV_HIGH(arg1), c);
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tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0);
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}
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} else {
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tcg_gen_shli_i32(s, TCGV_HIGH(ret), TCGV_LOW(arg1), c);
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tcg_gen_movi_i32(s, TCGV_LOW(ret), 0);
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}
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} else {
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TCGv_i32 t0, t1;
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t0 = tcg_temp_new_i32(s);
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t1 = tcg_temp_new_i32(s);
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if (right) {
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tcg_gen_shli_i32(s, t0, TCGV_HIGH(arg1), 32 - c);
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if (arith)
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tcg_gen_sari_i32(s, t1, TCGV_HIGH(arg1), c);
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else
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tcg_gen_shri_i32(s, t1, TCGV_HIGH(arg1), c);
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tcg_gen_shri_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), c);
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tcg_gen_or_i32(s, TCGV_LOW(ret), TCGV_LOW(ret), t0);
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tcg_gen_mov_i32(s, TCGV_HIGH(ret), t1);
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} else {
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tcg_gen_shri_i32(s, t0, TCGV_LOW(arg1), 32 - c);
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/* Note: ret can be the same as arg1, so we use t1 */
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tcg_gen_shli_i32(s, t1, TCGV_LOW(arg1), c);
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tcg_gen_shli_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
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tcg_gen_or_i32(s, TCGV_HIGH(ret), TCGV_HIGH(ret), t0);
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tcg_gen_mov_i32(s, TCGV_LOW(ret), t1);
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}
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tcg_temp_free_i32(s, t0);
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tcg_temp_free_i32(s, t1);
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}
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}
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#endif
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static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)
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{
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switch (op & MO_SIZE) {
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case MO_8:
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op &= ~MO_BSWAP;
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break;
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case MO_16:
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break;
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case MO_32:
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if (!is64) {
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op &= ~MO_SIGN;
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}
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break;
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case MO_64:
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if (!is64) {
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tcg_abort();
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}
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break;
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}
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if (st) {
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op &= ~MO_SIGN;
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}
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return op;
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}
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// Unicorn engine
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// check if the last memory access was invalid
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// if so, we jump to the block epilogue to quit immediately.
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void check_exit_request(TCGContext *tcg_ctx)
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{
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TCGv_i32 flag;
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flag = tcg_temp_new_i32(tcg_ctx);
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tcg_gen_ld_i32(tcg_ctx, flag, tcg_ctx->cpu_env,
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offsetof(CPUState, tcg_exit_req) - ENV_OFFSET);
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tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, flag, 0, tcg_ctx->exitreq_label);
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tcg_temp_free_i32(tcg_ctx, flag);
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}
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void tcg_gen_qemu_ld_i32(struct uc_struct *uc, TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
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{
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TCGContext *tcg_ctx = uc->tcg_ctx;
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memop = tcg_canonicalize_memop(memop, 0, 0);
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*tcg_ctx->gen_opc_ptr++ = INDEX_op_qemu_ld_i32;
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tcg_add_param_i32(tcg_ctx, val);
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tcg_add_param_tl(tcg_ctx, addr);
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*tcg_ctx->gen_opparam_ptr++ = memop;
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*tcg_ctx->gen_opparam_ptr++ = idx;
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check_exit_request(tcg_ctx);
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}
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void tcg_gen_qemu_st_i32(struct uc_struct *uc, TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
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{
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TCGContext *tcg_ctx = uc->tcg_ctx;
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memop = tcg_canonicalize_memop(memop, 0, 1);
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*tcg_ctx->gen_opc_ptr++ = INDEX_op_qemu_st_i32;
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tcg_add_param_i32(tcg_ctx, val);
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tcg_add_param_tl(tcg_ctx, addr);
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*tcg_ctx->gen_opparam_ptr++ = memop;
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*tcg_ctx->gen_opparam_ptr++ = idx;
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check_exit_request(tcg_ctx);
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}
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void tcg_gen_qemu_ld_i64(struct uc_struct *uc, TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
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{
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TCGContext *tcg_ctx = uc->tcg_ctx;
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memop = tcg_canonicalize_memop(memop, 1, 0);
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#if TCG_TARGET_REG_BITS == 32
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if ((memop & MO_SIZE) < MO_64) {
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tcg_gen_qemu_ld_i32(uc, TCGV_LOW(val), addr, idx, memop);
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if (memop & MO_SIGN) {
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tcg_gen_sari_i32(tcg_ctx, TCGV_HIGH(val), TCGV_LOW(val), 31);
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} else {
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tcg_gen_movi_i32(tcg_ctx, TCGV_HIGH(val), 0);
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}
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check_exit_request(tcg_ctx);
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return;
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}
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#endif
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*tcg_ctx->gen_opc_ptr++ = INDEX_op_qemu_ld_i64;
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tcg_add_param_i64(tcg_ctx, val);
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tcg_add_param_tl(tcg_ctx, addr);
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*tcg_ctx->gen_opparam_ptr++ = memop;
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*tcg_ctx->gen_opparam_ptr++ = idx;
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check_exit_request(tcg_ctx);
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}
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void tcg_gen_qemu_st_i64(struct uc_struct *uc, TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
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{
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TCGContext *tcg_ctx = uc->tcg_ctx;
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memop = tcg_canonicalize_memop(memop, 1, 1);
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#if TCG_TARGET_REG_BITS == 32
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if ((memop & MO_SIZE) < MO_64) {
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tcg_gen_qemu_st_i32(uc, TCGV_LOW(val), addr, idx, memop);
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check_exit_request(tcg_ctx);
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return;
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}
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#endif
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*tcg_ctx->gen_opc_ptr++ = INDEX_op_qemu_st_i64;
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tcg_add_param_i64(tcg_ctx, val);
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tcg_add_param_tl(tcg_ctx, addr);
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*tcg_ctx->gen_opparam_ptr++ = memop;
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*tcg_ctx->gen_opparam_ptr++ = idx;
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check_exit_request(tcg_ctx);
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}
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static void tcg_reg_alloc_start(TCGContext *s)
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static void tcg_reg_alloc_start(TCGContext *s)
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{
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{
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int i;
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int i;
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@ -830,9 +830,6 @@ void tcg_add_target_add_op_defs(TCGContext *s, const TCGTargetOpDef *tdefs);
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void tcg_gen_callN(TCGContext *s, void *func,
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void tcg_gen_callN(TCGContext *s, void *func,
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TCGArg ret, int nargs, TCGArg *args);
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TCGArg ret, int nargs, TCGArg *args);
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void tcg_gen_shifti_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1,
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int c, int right, int arith);
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TCGArg *tcg_optimize(TCGContext *s, uint16_t *tcg_opc_ptr, TCGArg *args,
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TCGArg *tcg_optimize(TCGContext *s, uint16_t *tcg_opc_ptr, TCGArg *args,
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TCGOpDef *tcg_op_def);
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TCGOpDef *tcg_op_def);
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@ -1025,8 +1022,6 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
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# define helper_ret_stq_mmu helper_le_stq_mmu
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# define helper_ret_stq_mmu helper_le_stq_mmu
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#endif
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#endif
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void check_exit_request(TCGContext *tcg_ctx);
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#endif /* CONFIG_SOFTMMU */
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#endif /* CONFIG_SOFTMMU */
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#endif /* TCG_H */
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#endif /* TCG_H */
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