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target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF

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The v8 ARM ARM defines that unused spaces in the ID_AA64* system
register ranges are Reserved and must RAZ, rather than being UNDEF.
Implement this.

In particular, ARM v8.2 adds a new feature register ID_AA64MMFR2,
and newer versions of the Linux kernel will attempt to read this,
which causes them not to boot up on versions of QEMU missing this fix.

Since the encoding .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6
is actually defined in ARMv8 (as ID_MMFR4), we give it an entry in
the ARMCPU struct so CPUs can override it, though since none do
this too will just RAZ.

Backports commit e20d84c1407d43d5a2e2ac95dbb46db3b0af8f9f from qemu
This commit is contained in:
Peter Maydell 2018-02-20 22:49:34 -05:00 committed by Lioncash
parent 66c4bd02eb
commit 20712bcb9a
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 60 additions and 1 deletions
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1
qemu/target-arm/cpu-qom.h
View file

@ -154,6 +154,7 @@ typedef struct ARMCPU {
uint32_t id_mmfr1;
uint32_t id_mmfr2;
uint32_t id_mmfr3;
uint32_t id_mmfr4;
uint32_t id_isar0;
uint32_t id_isar1;
uint32_t id_isar2;

60
qemu/target-arm/helper.c
View file

@ -3803,12 +3803,28 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, not_v7_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_V8)) {
/* AArch64 ID registers, which all have impdef reset values */
/* AArch64 ID registers, which all have impdef reset values.
* Note that within the ID register ranges the unused slots
* must all RAZ, not UNDEF; future architecture versions may
* define new registers here.
*/
ARMCPRegInfo v8_idregs[] = {
{ "ID_AA64PFR0_EL1", 0,0,4, 3,0,0, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64pfr0 },
{ "ID_AA64PFR1_EL1", 0,0,4, 3,0,1, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64pfr1},
{ "ID_AA64PFR2_EL1_RESERVED", 0,0,4, 3,0,2, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64PFR3_EL1_RESERVED", 0,0,4, 3,0,3, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0,},
{ "ID_AA64PFR4_EL1_RESERVED", 0,0,4, 3,0,4, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64PFR5_EL1_RESERVED", 0,0,4, 3,0,5, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64PFR6_EL1_RESERVED", 0,0,4, 3,0,6, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64PFR7_EL1_RESERVED", 0,0,4, 3,0,7, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64DFR0_EL1", 0,0,5, 3,0,0, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL1_R, 0, NULL,
/* We mask out the PMUVer field, because we don't currently
@ -3819,24 +3835,66 @@ void register_cp_regs_for_features(ARMCPU *cpu)
cpu->id_aa64dfr0 & ~0xf00 },
{ "ID_AA64DFR1_EL1", 0,0,5, 3,0,1, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64dfr1 },
{ "ID_AA64DFR2_EL1_RESERVED", 0,0,5, 3,0,2, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64DFR3_EL1_RESERVED", 0,0,5, 3,0,3, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64AFR0_EL1", 0,0,5, 3,0,4, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64afr0 },
{ "ID_AA64AFR1_EL1", 0,0,5, 3,0,5, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64afr1 },
{ "ID_AA64AFR2_EL1_RESERVED", 0,0,5, 3,0,6, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64AFR3_EL1_RESERVED", 0,0,5, 3,0,7, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64ISAR0_EL1", 0,0,6, 3,0,0, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64isar0 },
{ "ID_AA64ISAR1_EL1", 0,0,6, 3,0,1, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64isar1 },
{ "ID_AA64ISAR2_EL1_RESERVED", 0,0,6, 3,0,2, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64ISAR3_EL1_RESERVED", 0,0,6, 3,0,3, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64ISAR4_EL1_RESERVED", 0,0,6, 3,0,4, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64ISAR5_EL1_RESERVED", 0,0,6, 3,0,5, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64ISAR6_EL1_RESERVED", 0,0,6, 3,0,6, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64ISAR7_EL1_RESERVED", 0,0,6, 3,0,7, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64MMFR0_EL1", 0,0,7, 3,0,0, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64mmfr0 },
{ "ID_AA64MMFR1_EL1", 0,0,7, 3,0,1, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64mmfr1 },
{ "ID_AA64MMFR2_EL1_RESERVED", 0,0,7, 3,0,2, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64MMFR3_EL1_RESERVED", 0,0,7, 3,0,3, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64MMFR4_EL1_RESERVED", 0,0,7, 3,0,4, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64MMFR5_EL1_RESERVED", 0,0,7, 3,0,5, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64MMFR6_EL1_RESERVED", 0,0,7, 3,0,6, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "ID_AA64MMFR7_EL1_RESERVED", 0,0,7, 3,0,7, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "MVFR0_EL1", 0,0,3, 3,0,0, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL1_R, 0, NULL, cpu->mvfr0 },
{ "MVFR1_EL1", 0,0,3, 3,0,1, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL1_R, 0, NULL, cpu->mvfr1 },
{ "MVFR2_EL1", 0,0,3, 3,0,2, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL1_R, 0, NULL, cpu->mvfr2 },
{ "MVFR3_EL1_RESERVED", 0,0,3, 3,0,3, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "MVFR4_EL1_RESERVED", 0,0,3, 3,0,4, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "MVFR5_EL1_RESERVED", 0,0,3, 3,0,5, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "MVFR6_EL1_RESERVED", 0,0,3, 3,0,6, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "MVFR7_EL1_RESERVED", 0,0,3, 3,0,7, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },
{ "PMCEID0", 15,9,12, 0,0,6, ARM_CP_STATE_AA32, ARM_CP_CONST,
PL0_R, 0, NULL, cpu->pmceid0, 0, {0, 0},
pmreg_access },