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target/arm: Implement AArch32 ERET instruction

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ARMv7VE introduced the ERET instruction, which is necessary to
return from an exception taken to Hyp mode. Implement this.
In A32 encoding it is a completely new encoding; in T32 it
is an adjustment of the behaviour of the existing
"SUBS PC, LR, #<imm8>" instruction.

Backports commit 55c544ed2709bd202e71e77ddfe3ea0327852211 from qemu
This commit is contained in:
Peter Maydell 2018-08-22 12:56:11 -04:00 committed by Lioncash
parent 8c41572624
commit 214dadf7e7
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 29 additions and 2 deletions
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31
qemu/target/arm/translate.c
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@ -9080,6 +9080,25 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
tcg_temp_free_i32(tcg_ctx, tmp2);
store_reg(s, rd, tmp);
break;
case 0x6: /* ERET */
if (op1 != 3) {
goto illegal_op;
}
if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) {
goto illegal_op;
}
if ((insn & 0x000fff0f) != 0x0000000e) {
/* UNPREDICTABLE; we choose to UNDEF */
goto illegal_op;
}
if (s->current_el == 2) {
tmp = load_cpu_field(s->uc, elr_el[2]);
} else {
tmp = load_reg(s, 14);
}
gen_exception_return(s, tmp);
break;
case 7:
{
int imm16 = extract32(insn, 0, 4) | (extract32(insn, 8, 12) << 4);
@ -11333,8 +11352,16 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
if (rn != 14 || rd != 15) {
goto illegal_op;
}
tmp = load_reg(s, rn);
tcg_gen_subi_i32(tcg_ctx, tmp, tmp, insn & 0xff);
if (s->current_el == 2) {
/* ERET from Hyp uses ELR_Hyp, not LR */
if (insn & 0xff) {
goto illegal_op;
}
tmp = load_cpu_field(s->uc, elr_el[2]);
} else {
tmp = load_reg(s, rn);
tcg_gen_subi_i32(tcg_ctx, tmp, tmp, insn & 0xff);
}
gen_exception_return(s, tmp);
break;
case 6: /* MRS */