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target/arm: Add TTBR1_EL2

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At the same time, add writefn to TTBR0_EL2 and TCR_EL2.
A later patch will update any ASID therein.

Backports commit ed30da8eee6906032b38a84e4807e2142b09d8ec from qemu
This commit is contained in:
Richard Henderson 2020-03-21 13:47:51 -04:00 committed by Lioncash
parent 35508d46c7
commit 215b4a9851
1 changed files with 12 additions and 1 deletions
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13
qemu/target/arm/helper.c
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@ -3307,6 +3307,13 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
raw_write(env, ri, value); raw_write(env, ri, value);
} }
static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* TODO: There are ASID fields in here with HCR_EL2.E2H */
raw_write(env, ri, value);
}
static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
@ -4767,7 +4774,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
{ .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
.access = PL2_RW, .resetvalue = 0, .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write,
.fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
{ .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
.access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
@ -5911,6 +5918,10 @@ static const ARMCPRegInfo vhe_reginfo[] = {
.opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
.access = PL2_RW, .access = PL2_RW,
.fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) }, .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
{ .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
.access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
.fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) },
REGINFO_SENTINEL REGINFO_SENTINEL
}; };