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target-mips: indicate presence of IEEE 754-2008 FPU in R6/R5+MSA CPUs
MIPS Release 6 and MIPS SIMD Architecture make it mandatory to have IEEE 754-2008 FPU which is indicated by CP1 FIR.HAS2008, FCSR.ABS2008 and FCSR.NAN2008 bits set to 1. In QEMU we still keep these bits cleared as there is no 2008-NaN support. However, this now causes problems preventing from running R6 Linux with the v4.5 kernel. Kernel refuses to execute 2008-NaN ELFs on a CPU whose FPU does not support 2008-NaN encoding: (...) VFS: Mounted root (ext4 filesystem) readonly on device 8:0. devtmpfs: mounted Freeing unused kernel memory: 256K (ffffffff806f0000 - ffffffff80730000) request_module: runaway loop modprobe binfmt-464c Starting init: /sbin/init exists but couldn't execute it (error -8) request_module: runaway loop modprobe binfmt-464c Starting init: /bin/sh exists but couldn't execute it (error -8) Kernel panic - not syncing: No working init found. Try passing init= option to kernel. See Linux Documentation/init.txt for guidance. Therefore always indicate presence of 2008-NaN support in R6 as well as in R5+MSA CPUs, even though this feature is not yet supported by MIPS in QEMU. Backports commit ba5c79f26221c0fd7139c883a34a4e75d993f732 from qemu
This commit is contained in:
parent
eb29ff04ca
commit
224cbb008a
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@ -100,6 +100,7 @@ struct CPUMIPSFPUContext {
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uint32_t fcr0;
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uint32_t fcr0;
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#define FCR0_FREP 29
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#define FCR0_FREP 29
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#define FCR0_UFRP 28
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#define FCR0_UFRP 28
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#define FCR0_HAS2008 23
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#define FCR0_F64 22
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#define FCR0_F64 22
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#define FCR0_L 21
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#define FCR0_L 21
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#define FCR0_W 20
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#define FCR0_W 20
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@ -111,6 +112,8 @@ struct CPUMIPSFPUContext {
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#define FCR0_REV 0
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#define FCR0_REV 0
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/* fcsr */
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/* fcsr */
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uint32_t fcr31;
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uint32_t fcr31;
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#define FCR31_ABS2008 19
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#define FCR31_NAN2008 18
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#define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
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#define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
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#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
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#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
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#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
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#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
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@ -20263,6 +20263,7 @@ void cpu_state_reset(CPUMIPSState *env)
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env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask;
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env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask;
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env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
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env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
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env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
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env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
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env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
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env->msair = env->cpu_model->MSAIR;
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env->msair = env->cpu_model->MSAIR;
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env->insn_flags = env->cpu_model->insn_flags;
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env->insn_flags = env->cpu_model->insn_flags;
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@ -84,6 +84,7 @@ struct mips_def_t {
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int32_t CP0_TCStatus_rw_bitmask;
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int32_t CP0_TCStatus_rw_bitmask;
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int32_t CP0_SRSCtl;
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int32_t CP0_SRSCtl;
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int32_t CP1_fcr0;
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int32_t CP1_fcr0;
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int32_t CP1_fcr31;
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int32_t MSAIR;
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int32_t MSAIR;
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int32_t SEGBITS;
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int32_t SEGBITS;
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int32_t PABITS;
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int32_t PABITS;
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@ -128,7 +129,8 @@ static const mips_def_t mips_defs[] =
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0x1278FF17,
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0x1278FF17,
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0,
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0,
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0,
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0,
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0,
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0, // CP1_fcr0
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0, // CP1_fcr31
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0,
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0,
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32,
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32,
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32,
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32,
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@ -152,7 +154,7 @@ static const mips_def_t mips_defs[] =
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0,0,
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0,0,
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0,
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0,
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0,
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0,
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0,
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0,
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4,
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4,
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32,
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32,
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@ -161,7 +163,8 @@ static const mips_def_t mips_defs[] =
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0,
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0,
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0,
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0,
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0,
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0, // CP1_fcr0
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0, // CP1_fcr31
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0,
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0,
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32,
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32,
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32,
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32,
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@ -190,7 +193,8 @@ static const mips_def_t mips_defs[] =
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0x1278FF17,
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0x1278FF17,
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0,
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0,
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0,
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0,
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0,
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0, // CP1_fcr0
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0, // CP1_fcr31
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0,
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0,
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32,
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32,
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32,
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32,
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@ -219,7 +223,8 @@ static const mips_def_t mips_defs[] =
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0x1258FF17,
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0x1258FF17,
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0,
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0,
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0,
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0,
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0,
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0, // CP1_fcr0
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0, // CP1_fcr31
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0,
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0,
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32,
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32,
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32,
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32,
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@ -249,7 +254,8 @@ static const mips_def_t mips_defs[] =
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0x1278FF17,
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0x1278FF17,
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0,
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0,
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0,
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0,
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0,
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0, // CP1_fcr0
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0, // CP1_fcr31
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0,
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0,
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32,
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32,
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32,
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32,
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@ -279,7 +285,8 @@ static const mips_def_t mips_defs[] =
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0x1258FF17,
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0x1258FF17,
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0,
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0,
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0,
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0,
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0,
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0, // CP1_fcr0
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0, // CP1_fcr31
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0,
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0,
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32,
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32,
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32,
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32,
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@ -310,6 +317,8 @@ static const mips_def_t mips_defs[] =
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0x1278FF1F,
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0x1278FF1F,
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0,
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0,
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0,
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0,
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0, // CP1_fcr0
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0, // CP1_fcr31
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0,
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0,
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32,
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32,
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32,
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32,
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@ -343,6 +352,7 @@ static const mips_def_t mips_defs[] =
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(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
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(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
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0,
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0,
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0,
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32,
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32,
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32,
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32,
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0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
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0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
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@ -378,6 +388,7 @@ static const mips_def_t mips_defs[] =
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32,
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32,
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(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
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(1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
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0,
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0x3fffffff,
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0x3fffffff,
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(1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
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(1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
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(0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
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(0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
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@ -423,6 +434,7 @@ static const mips_def_t mips_defs[] =
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(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
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(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
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0,
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0,
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0,
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32,
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32,
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32,
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32,
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0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
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0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
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@ -450,7 +462,8 @@ static const mips_def_t mips_defs[] =
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0x1258FF17,
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0x1258FF17,
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0,
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0,
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0,
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0,
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0,
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0, // CP1_fcr0
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0, // CP1_fcr31
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0,
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0,
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32,
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32,
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32,
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32,
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@ -480,7 +493,8 @@ static const mips_def_t mips_defs[] =
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0x1278FF17,
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0x1278FF17,
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0,
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0,
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0,
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0,
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0,
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0, // CP1_fcr0
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0, // CP1_fcr31
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0,
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0,
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32,
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32,
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32,
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32,
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@ -523,9 +537,10 @@ static const mips_def_t mips_defs[] =
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0x3C68FF1F,
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0x3C68FF1F,
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0,
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0,
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0,
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0,
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(1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_F64) |
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(1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) |
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(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
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(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_S) | (0x03 << FCR0_PRID),
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(1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
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(1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
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0,
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0,
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32,
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32,
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40,
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40,
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@ -564,9 +579,10 @@ static const mips_def_t mips_defs[] =
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0x3058FF1F,
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0x3058FF1F,
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0,
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0,
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0,
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0,
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(1 << FCR0_FREP) | (1 << FCR0_F64) | (1 << FCR0_L) |
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(1 << FCR0_FREP) | (1 << FCR0_F64) | (1 << FCR0_HAS2008) | (1 << FCR0_L) |
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(1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
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(1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
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(0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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(0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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(1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
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0,
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0,
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32,
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32,
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32,
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32,
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@ -604,6 +620,7 @@ static const mips_def_t mips_defs[] =
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/* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
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/* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
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(0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
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(0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
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0,
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0,
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0,
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40,
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40,
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36,
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36,
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0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
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0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
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@ -632,6 +649,7 @@ static const mips_def_t mips_defs[] =
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/* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
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/* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
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(0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
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(0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
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0,
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0,
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0,
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40,
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40,
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32,
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32,
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0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
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0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
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@ -660,7 +678,8 @@ static const mips_def_t mips_defs[] =
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0x12F8FFFF,
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0x12F8FFFF,
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0,
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0,
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0,
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0,
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0,
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0, // CP1_fcr0
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0, // CP1_fcr31
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0,
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0,
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42,
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42,
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36,
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36,
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@ -683,7 +702,7 @@ static const mips_def_t mips_defs[] =
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0,0,
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0,0,
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0,
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0,
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0,
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0,
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0,
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0,
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4,
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4,
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32,
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32,
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@ -695,6 +714,7 @@ static const mips_def_t mips_defs[] =
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(1 << FCR0_D) | (1 << FCR0_S) |
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(1 << FCR0_D) | (1 << FCR0_S) |
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(0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
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(0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
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0,
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0,
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0,
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42,
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42,
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36,
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36,
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0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
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0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
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@ -730,6 +750,7 @@ static const mips_def_t mips_defs[] =
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(1 << FCR0_D) | (1 << FCR0_S) |
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(1 << FCR0_D) | (1 << FCR0_S) |
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(0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
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(0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
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0,
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0,
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0,
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40,
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40,
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36,
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36,
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0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
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0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
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@ -764,6 +785,7 @@ static const mips_def_t mips_defs[] =
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(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
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(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
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(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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0,
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0,
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0,
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42,
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42,
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36,
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36,
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0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
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0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
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@ -802,9 +824,10 @@ static const mips_def_t mips_defs[] =
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0x30D8FFFF,
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0x30D8FFFF,
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0,
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0,
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0,
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0,
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(1 << FCR0_FREP) | (1 << FCR0_F64) | (1 << FCR0_L) |
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(1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
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(1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
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(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
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(0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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(1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
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0,
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0,
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48,
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48,
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48,
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48,
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@ -839,7 +862,8 @@ static const mips_def_t mips_defs[] =
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0x12F8FFFF,
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0x12F8FFFF,
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||||||
0,
|
0,
|
||||||
0,
|
0,
|
||||||
0,
|
0, // CP1_fcr0
|
||||||
|
0, // CP1_fcr31
|
||||||
0,
|
0,
|
||||||
42,
|
42,
|
||||||
36,
|
36,
|
||||||
|
@ -875,6 +899,7 @@ static const mips_def_t mips_defs[] =
|
||||||
(1 << FCR0_D) | (1 << FCR0_S) |
|
(1 << FCR0_D) | (1 << FCR0_S) |
|
||||||
(0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
|
(0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
|
||||||
0,
|
0,
|
||||||
|
0,
|
||||||
42,
|
42,
|
||||||
36,
|
36,
|
||||||
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
|
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
|
||||||
|
@ -904,6 +929,7 @@ static const mips_def_t mips_defs[] =
|
||||||
0,
|
0,
|
||||||
(0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
|
(0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
|
||||||
0,
|
0,
|
||||||
|
0,
|
||||||
40,
|
40,
|
||||||
40,
|
40,
|
||||||
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
|
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
|
||||||
|
@ -933,6 +959,7 @@ static const mips_def_t mips_defs[] =
|
||||||
0,
|
0,
|
||||||
(0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
|
(0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
|
||||||
0,
|
0,
|
||||||
|
0,
|
||||||
40,
|
40,
|
||||||
40,
|
40,
|
||||||
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
|
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
|
||||||
|
@ -968,6 +995,7 @@ static const mips_def_t mips_defs[] =
|
||||||
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
|
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
|
||||||
(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
|
(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
|
||||||
0,
|
0,
|
||||||
|
0,
|
||||||
42,
|
42,
|
||||||
/* The architectural limit is 59, but we have hardcoded 36 bit
|
/* The architectural limit is 59, but we have hardcoded 36 bit
|
||||||
in some places...
|
in some places...
|
||||||
|
@ -977,7 +1005,6 @@ static const mips_def_t mips_defs[] =
|
||||||
CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
|
CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
|
||||||
MMU_TYPE_R4000,
|
MMU_TYPE_R4000,
|
||||||
},
|
},
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue