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target-arm: Implement FPEXC32_EL2 system register
The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3, and allows those exception levels to read and write the FPEXC register for a lower exception level that is using AArch32. Backports commit 03fbf20f4da58f41998dc10ec7542f65d37ba759 from qemu
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@ -2592,6 +2592,17 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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tlb_flush(CPU(cpu), 1);
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}
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static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) {
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return CP_ACCESS_TRAP_EL2;
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}
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if (env->cp15.cptr_el[3] & CPTR_TFP) {
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return CP_ACCESS_TRAP_EL3;
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}
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return CP_ACCESS_OK;
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}
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static const ARMCPRegInfo v8_cp_reginfo[] = {
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/* Minimal set of EL0-visible registers. This will need to be expanded
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* significantly for system emulation of AArch64 CPUs.
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@ -2803,6 +2814,9 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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{ "SPSel", 0,4,2, 3,0,0, ARM_CP_STATE_AA64,
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ARM_CP_NO_RAW, PL1_RW, 0, NULL, 0, 0, {0, 0},
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NULL, spsel_read, spsel_write },
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{ "FPEXC32_EL2", 0,5,3, 3,4,0, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
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PL2_RW, 0, NULL, 0, offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), {0, 0},
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fpexc32_access },
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REGINFO_SENTINEL
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};
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