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target-arm: Implement FPEXC32_EL2 system register

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The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3,
and allows those exception levels to read and write the FPEXC
register for a lower exception level that is using AArch32.

Backports commit 03fbf20f4da58f41998dc10ec7542f65d37ba759 from qemu
This commit is contained in:
Peter Maydell 2018-02-18 22:52:51 -05:00 committed by Lioncash
parent f4ae64e78a
commit 22dadac875
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 14 additions and 0 deletions
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14
qemu/target-arm/helper.c
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@ -2592,6 +2592,17 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
tlb_flush(CPU(cpu), 1); tlb_flush(CPU(cpu), 1);
} }
static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) {
return CP_ACCESS_TRAP_EL2;
}
if (env->cp15.cptr_el[3] & CPTR_TFP) {
return CP_ACCESS_TRAP_EL3;
}
return CP_ACCESS_OK;
}
static const ARMCPRegInfo v8_cp_reginfo[] = { static const ARMCPRegInfo v8_cp_reginfo[] = {
/* Minimal set of EL0-visible registers. This will need to be expanded /* Minimal set of EL0-visible registers. This will need to be expanded
* significantly for system emulation of AArch64 CPUs. * significantly for system emulation of AArch64 CPUs.
@ -2803,6 +2814,9 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ "SPSel", 0,4,2, 3,0,0, ARM_CP_STATE_AA64, { "SPSel", 0,4,2, 3,0,0, ARM_CP_STATE_AA64,
ARM_CP_NO_RAW, PL1_RW, 0, NULL, 0, 0, {0, 0}, ARM_CP_NO_RAW, PL1_RW, 0, NULL, 0, 0, {0, 0},
NULL, spsel_read, spsel_write }, NULL, spsel_read, spsel_write },
{ "FPEXC32_EL2", 0,5,3, 3,4,0, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), {0, 0},
fpexc32_access },
REGINFO_SENTINEL REGINFO_SENTINEL
}; };