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target-i386: Use clz and ctz opcodes
Backports commit e5143c90883cd32a432eb793cdcce6bee747834a from qemu
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@ -203,14 +203,6 @@ DEF_HELPER_FLAGS_3(xsetbv, TCG_CALL_NO_WG, void, env, i32, i64)
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DEF_HELPER_FLAGS_2(rdpkru, TCG_CALL_NO_WG, i64, env, i32)
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DEF_HELPER_FLAGS_3(wrpkru, TCG_CALL_NO_WG, void, env, i32, i64)
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DEF_HELPER_FLAGS_1(clz_x86, TCG_CALL_NO_RWG_SE, tl, tl)
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#ifdef TARGET_I386
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#define helper_clz helper_clz_x86
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#define gen_helper_clz gen_helper_clz_x86
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#endif
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DEF_HELPER_FLAGS_1(ctz, TCG_CALL_NO_RWG_SE, tl, tl)
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DEF_HELPER_FLAGS_2(pdep, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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DEF_HELPER_FLAGS_2(pext, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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@ -417,17 +417,6 @@ void helper_idivq_EAX(CPUX86State *env, target_ulong t0)
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# define clztl clz64
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#endif
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/* bit operations */
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target_ulong helper_ctz(target_ulong t0)
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{
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return ctztl(t0);
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}
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target_ulong helper_clz_x86(target_ulong t0)
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{
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return clztl(t0);
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}
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target_ulong helper_pdep(target_ulong src, target_ulong mask)
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{
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target_ulong dest = 0;
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@ -7481,21 +7481,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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? s->cpuid_ext3_features & CPUID_EXT3_ABM
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: s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)) {
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int size = 8 << ot;
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/* For lzcnt/tzcnt, C bit is defined related to the input. */
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tcg_gen_mov_tl(tcg_ctx, cpu_cc_src, cpu_T0);
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if (b & 1) {
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/* For lzcnt, reduce the target_ulong result by the
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number of zeros that we expect to find at the top. */
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gen_helper_clz(tcg_ctx, cpu_T0, cpu_T0);
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tcg_gen_clzi_tl(tcg_ctx, cpu_T0, cpu_T0, TARGET_LONG_BITS);
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tcg_gen_subi_tl(tcg_ctx, cpu_T0, cpu_T0, TARGET_LONG_BITS - size);
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} else {
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/* For tzcnt, a zero input must return the operand size:
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force all bits outside the operand size to 1. */
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target_ulong mask = (target_ulong)-2 << (size - 1);
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tcg_gen_ori_tl(tcg_ctx, cpu_T0, cpu_T0, mask);
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gen_helper_ctz(tcg_ctx, cpu_T0, cpu_T0);
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/* For tzcnt, a zero input must return the operand size. */
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tcg_gen_ctzi_tl(tcg_ctx, cpu_T0, cpu_T0, size);
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}
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/* For lzcnt/tzcnt, C and Z bits are defined and are
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related to the result. */
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/* For lzcnt/tzcnt, Z bit is defined related to the result. */
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gen_op_update1_cc(tcg_ctx);
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set_cc_op(s, CC_OP_BMILGB + ot);
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} else {
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@ -7503,20 +7500,20 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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to the input and not the result. */
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tcg_gen_mov_tl(tcg_ctx, cpu_cc_dst, cpu_T0);
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set_cc_op(s, CC_OP_LOGICB + ot);
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/* ??? The manual says that the output is undefined when the
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input is zero, but real hardware leaves it unchanged, and
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real programs appear to depend on that. Accomplish this
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by passing the output as the value to return upon zero. */
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if (b & 1) {
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/* For bsr, return the bit index of the first 1 bit,
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not the count of leading zeros. */
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gen_helper_clz(tcg_ctx, cpu_T0, cpu_T0);
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tcg_gen_xori_tl(tcg_ctx, cpu_T1, cpu_regs[reg], TARGET_LONG_BITS - 1);
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tcg_gen_clz_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_T1);
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tcg_gen_xori_tl(tcg_ctx, cpu_T0, cpu_T0, TARGET_LONG_BITS - 1);
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} else {
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gen_helper_ctz(tcg_ctx, cpu_T0, cpu_T0);
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tcg_gen_ctz_tl(tcg_ctx, cpu_T0, cpu_T0, cpu_regs[reg]);
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}
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/* ??? The manual says that the output is undefined when the
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input is zero, but real hardware leaves it unchanged, and
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real programs appear to depend on that. */
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tcg_gen_movi_tl(tcg_ctx, cpu_tmp0, 0);
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tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, cpu_T0, cpu_cc_dst, cpu_tmp0,
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cpu_regs[reg], cpu_T0);
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}
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gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0);
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break;
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