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tcg/i386: Support INDEX_op_dup2_vec for -m32

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Unknown why -m32 was passing with gcc but not clang; it should have
failed for both. This would be used for tcg_gen_dup_i64_vec, and
visible with the right TB and an aarch64 guest.

Backports commit 7f34ed4bcdfda55f978f51aadca64aa970c9f4b6 from qemu
This commit is contained in:
Richard Henderson 2018-03-17 19:54:34 -04:00 committed by Lioncash
parent e9eee21efd
commit 2310bd4887
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 9 additions and 0 deletions
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9
qemu/tcg/i386/tcg-target.inc.c
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@ -2796,6 +2796,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_x86_packus_vec:
insn = packus_insn[vece];
goto gen_simd;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_dup2_vec:
/* Constraints have already placed both 32-bit inputs in xmm regs. */
insn = OPC_PUNPCKLDQ;
goto gen_simd;
#endif
gen_simd:
tcg_debug_assert(insn != OPC_UD2);
if (type == TCG_TYPE_V256) {
@ -3133,6 +3139,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_x86_vperm2i128_vec:
case INDEX_op_x86_punpckl_vec:
case INDEX_op_x86_punpckh_vec:
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_dup2_vec:
#endif
return &x_x_x;
case INDEX_op_dup_vec:
case INDEX_op_shli_vec: