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tcg/i386: Support INDEX_op_dup2_vec for -m32
Unknown why -m32 was passing with gcc but not clang; it should have failed for both. This would be used for tcg_gen_dup_i64_vec, and visible with the right TB and an aarch64 guest. Backports commit 7f34ed4bcdfda55f978f51aadca64aa970c9f4b6 from qemu
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@ -2796,6 +2796,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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case INDEX_op_x86_packus_vec:
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case INDEX_op_x86_packus_vec:
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insn = packus_insn[vece];
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insn = packus_insn[vece];
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goto gen_simd;
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goto gen_simd;
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#if TCG_TARGET_REG_BITS == 32
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case INDEX_op_dup2_vec:
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/* Constraints have already placed both 32-bit inputs in xmm regs. */
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insn = OPC_PUNPCKLDQ;
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goto gen_simd;
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#endif
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gen_simd:
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gen_simd:
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tcg_debug_assert(insn != OPC_UD2);
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tcg_debug_assert(insn != OPC_UD2);
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if (type == TCG_TYPE_V256) {
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if (type == TCG_TYPE_V256) {
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@ -3133,6 +3139,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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case INDEX_op_x86_vperm2i128_vec:
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case INDEX_op_x86_vperm2i128_vec:
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case INDEX_op_x86_punpckl_vec:
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case INDEX_op_x86_punpckl_vec:
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case INDEX_op_x86_punpckh_vec:
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case INDEX_op_x86_punpckh_vec:
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#if TCG_TARGET_REG_BITS == 32
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case INDEX_op_dup2_vec:
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#endif
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return &x_x_x;
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return &x_x_x;
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case INDEX_op_dup_vec:
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case INDEX_op_dup_vec:
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case INDEX_op_shli_vec:
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case INDEX_op_shli_vec:
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