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target/riscv: vector single-width averaging add and subtract

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Backports b7aee4819206cbb7adfdb624d4f2fa9918c25d43
This commit is contained in:
LIU Zhiwei 2021-03-05 09:25:07 -05:00 committed by Lioncash
parent 87db3eb130
commit 2343892c2e
7 changed files with 177 additions and 0 deletions
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16
qemu/header_gen.py
View file

@ -6892,6 +6892,22 @@ riscv_symbols = (
'helper_vssub_vx_h',
'helper_vssub_vx_w',
'helper_vssub_vx_d',
'helper_vaadd_vv_b',
'helper_vaadd_vv_h',
'helper_vaadd_vv_w',
'helper_vaadd_vv_d',
'helper_vasub_vv_b',
'helper_vasub_vv_h',
'helper_vasub_vv_w',
'helper_vasub_vv_d',
'helper_vaadd_vx_b',
'helper_vaadd_vx_h',
'helper_vaadd_vx_w',
'helper_vaadd_vx_d',
'helper_vasub_vx_b',
'helper_vasub_vx_h',
'helper_vasub_vx_w',
'helper_vasub_vx_d',
'pmp_hart_has_privs',
'pmpaddr_csr_read',
'pmpaddr_csr_write',

16
qemu/riscv32.h
View file

@ -4328,6 +4328,22 @@
#define helper_vssub_vx_h helper_vssub_vx_h_riscv32
#define helper_vssub_vx_w helper_vssub_vx_w_riscv32
#define helper_vssub_vx_d helper_vssub_vx_d_riscv32
#define helper_vaadd_vv_b helper_vaadd_vv_b_riscv32
#define helper_vaadd_vv_h helper_vaadd_vv_h_riscv32
#define helper_vaadd_vv_w helper_vaadd_vv_w_riscv32
#define helper_vaadd_vv_d helper_vaadd_vv_d_riscv32
#define helper_vasub_vv_b helper_vasub_vv_b_riscv32
#define helper_vasub_vv_h helper_vasub_vv_h_riscv32
#define helper_vasub_vv_w helper_vasub_vv_w_riscv32
#define helper_vasub_vv_d helper_vasub_vv_d_riscv32
#define helper_vaadd_vx_b helper_vaadd_vx_b_riscv32
#define helper_vaadd_vx_h helper_vaadd_vx_h_riscv32
#define helper_vaadd_vx_w helper_vaadd_vx_w_riscv32
#define helper_vaadd_vx_d helper_vaadd_vx_d_riscv32
#define helper_vasub_vx_b helper_vasub_vx_b_riscv32
#define helper_vasub_vx_h helper_vasub_vx_h_riscv32
#define helper_vasub_vx_w helper_vasub_vx_w_riscv32
#define helper_vasub_vx_d helper_vasub_vx_d_riscv32
#define pmp_hart_has_privs pmp_hart_has_privs_riscv32
#define pmpaddr_csr_read pmpaddr_csr_read_riscv32
#define pmpaddr_csr_write pmpaddr_csr_write_riscv32

16
qemu/riscv64.h
View file

@ -4328,6 +4328,22 @@
#define helper_vssub_vx_h helper_vssub_vx_h_riscv64
#define helper_vssub_vx_w helper_vssub_vx_w_riscv64
#define helper_vssub_vx_d helper_vssub_vx_d_riscv64
#define helper_vaadd_vv_b helper_vaadd_vv_b_riscv64
#define helper_vaadd_vv_h helper_vaadd_vv_h_riscv64
#define helper_vaadd_vv_w helper_vaadd_vv_w_riscv64
#define helper_vaadd_vv_d helper_vaadd_vv_d_riscv64
#define helper_vasub_vv_b helper_vasub_vv_b_riscv64
#define helper_vasub_vv_h helper_vasub_vv_h_riscv64
#define helper_vasub_vv_w helper_vasub_vv_w_riscv64
#define helper_vasub_vv_d helper_vasub_vv_d_riscv64
#define helper_vaadd_vx_b helper_vaadd_vx_b_riscv64
#define helper_vaadd_vx_h helper_vaadd_vx_h_riscv64
#define helper_vaadd_vx_w helper_vaadd_vx_w_riscv64
#define helper_vaadd_vx_d helper_vaadd_vx_d_riscv64
#define helper_vasub_vx_b helper_vasub_vx_b_riscv64
#define helper_vasub_vx_h helper_vasub_vx_h_riscv64
#define helper_vasub_vx_w helper_vasub_vx_w_riscv64
#define helper_vasub_vx_d helper_vasub_vx_d_riscv64
#define pmp_hart_has_privs pmp_hart_has_privs_riscv64
#define pmpaddr_csr_read pmpaddr_csr_read_riscv64
#define pmpaddr_csr_write pmpaddr_csr_write_riscv64

17
qemu/target/riscv/helper.h
View file

@ -715,3 +715,20 @@ DEF_HELPER_6(vssub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vaadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vaadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vaadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vaadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vasub_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vasub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vasub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vasub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vaadd_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vaadd_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vaadd_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vaadd_vx_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_d, void, ptr, ptr, tl, ptr, env, i32)

5
qemu/target/riscv/insn32.decode
View file

@ -413,6 +413,11 @@ vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm
vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm
vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm
vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm
vaadd_vv 100100 . ..... ..... 000 ..... 1010111 @r_vm
vaadd_vx 100100 . ..... ..... 100 ..... 1010111 @r_vm
vaadd_vi 100100 . ..... ..... 011 ..... 1010111 @r_vm
vasub_vv 100110 . ..... ..... 000 ..... 1010111 @r_vm
vasub_vx 100110 . ..... ..... 100 ..... 1010111 @r_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r

7
qemu/target/riscv/insn_trans/trans_rvv.inc.c
View file

@ -1684,3 +1684,10 @@ GEN_OPIVX_TRANS(vssubu_vx, opivx_check)
GEN_OPIVX_TRANS(vssub_vx, opivx_check)
GEN_OPIVI_TRANS(vsaddu_vi, 1, vsaddu_vx, opivx_check)
GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check)
/* Vector Single-Width Averaging Add and Subtract */
GEN_OPIVV_TRANS(vaadd_vv, opivv_check)
GEN_OPIVV_TRANS(vasub_vv, opivv_check)
GEN_OPIVX_TRANS(vaadd_vx, opivx_check)
GEN_OPIVX_TRANS(vasub_vx, opivx_check)
GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check)

100
qemu/target/riscv/vector_helper.c
View file

@ -2484,3 +2484,103 @@ GEN_VEXT_VX_RM(vssub_vx_b, 1, 1, clearb)
GEN_VEXT_VX_RM(vssub_vx_h, 2, 2, clearh)
GEN_VEXT_VX_RM(vssub_vx_w, 4, 4, clearl)
GEN_VEXT_VX_RM(vssub_vx_d, 8, 8, clearq)
/* Vector Single-Width Averaging Add and Subtract */
static inline uint8_t get_round(int vxrm, uint64_t v, uint8_t shift)
{
uint8_t d = extract64(v, shift, 1);
uint8_t d1;
uint64_t D1, D2;
if (shift == 0 || shift > 64) {
return 0;
}
d1 = extract64(v, shift - 1, 1);
D1 = extract64(v, 0, shift);
if (vxrm == 0) { /* round-to-nearest-up (add +0.5 LSB) */
return d1;
} else if (vxrm == 1) { /* round-to-nearest-even */
if (shift > 1) {
D2 = extract64(v, 0, shift - 1);
return d1 & ((D2 != 0) | d);
} else {
return d1 & d;
}
} else if (vxrm == 3) { /* round-to-odd (OR bits into LSB, aka "jam") */
return !d & (D1 != 0);
}
return 0; /* round-down (truncate) */
}
static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
{
int64_t res = (int64_t)a + b;
uint8_t round = get_round(vxrm, res, 1);
return (res >> 1) + round;
}
static inline int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
{
int64_t res = a + b;
uint8_t round = get_round(vxrm, res, 1);
int64_t over = (res ^ a) & (res ^ b) & INT64_MIN;
/* With signed overflow, bit 64 is inverse of bit 63. */
return ((res >> 1) ^ over) + round;
}
RVVCALL(OPIVV2_RM, vaadd_vv_b, OP_SSS_B, H1, H1, H1, aadd32)
RVVCALL(OPIVV2_RM, vaadd_vv_h, OP_SSS_H, H2, H2, H2, aadd32)
RVVCALL(OPIVV2_RM, vaadd_vv_w, OP_SSS_W, H4, H4, H4, aadd32)
RVVCALL(OPIVV2_RM, vaadd_vv_d, OP_SSS_D, H8, H8, H8, aadd64)
GEN_VEXT_VV_RM(vaadd_vv_b, 1, 1, clearb)
GEN_VEXT_VV_RM(vaadd_vv_h, 2, 2, clearh)
GEN_VEXT_VV_RM(vaadd_vv_w, 4, 4, clearl)
GEN_VEXT_VV_RM(vaadd_vv_d, 8, 8, clearq)
RVVCALL(OPIVX2_RM, vaadd_vx_b, OP_SSS_B, H1, H1, aadd32)
RVVCALL(OPIVX2_RM, vaadd_vx_h, OP_SSS_H, H2, H2, aadd32)
RVVCALL(OPIVX2_RM, vaadd_vx_w, OP_SSS_W, H4, H4, aadd32)
RVVCALL(OPIVX2_RM, vaadd_vx_d, OP_SSS_D, H8, H8, aadd64)
GEN_VEXT_VX_RM(vaadd_vx_b, 1, 1, clearb)
GEN_VEXT_VX_RM(vaadd_vx_h, 2, 2, clearh)
GEN_VEXT_VX_RM(vaadd_vx_w, 4, 4, clearl)
GEN_VEXT_VX_RM(vaadd_vx_d, 8, 8, clearq)
static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
{
int64_t res = (int64_t)a - b;
uint8_t round = get_round(vxrm, res, 1);
return (res >> 1) + round;
}
static inline int64_t asub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
{
int64_t res = (int64_t)a - b;
uint8_t round = get_round(vxrm, res, 1);
int64_t over = (res ^ a) & (a ^ b) & INT64_MIN;
/* With signed overflow, bit 64 is inverse of bit 63. */
return ((res >> 1) ^ over) + round;
}
RVVCALL(OPIVV2_RM, vasub_vv_b, OP_SSS_B, H1, H1, H1, asub32)
RVVCALL(OPIVV2_RM, vasub_vv_h, OP_SSS_H, H2, H2, H2, asub32)
RVVCALL(OPIVV2_RM, vasub_vv_w, OP_SSS_W, H4, H4, H4, asub32)
RVVCALL(OPIVV2_RM, vasub_vv_d, OP_SSS_D, H8, H8, H8, asub64)
GEN_VEXT_VV_RM(vasub_vv_b, 1, 1, clearb)
GEN_VEXT_VV_RM(vasub_vv_h, 2, 2, clearh)
GEN_VEXT_VV_RM(vasub_vv_w, 4, 4, clearl)
GEN_VEXT_VV_RM(vasub_vv_d, 8, 8, clearq)
RVVCALL(OPIVX2_RM, vasub_vx_b, OP_SSS_B, H1, H1, asub32)
RVVCALL(OPIVX2_RM, vasub_vx_h, OP_SSS_H, H2, H2, asub32)
RVVCALL(OPIVX2_RM, vasub_vx_w, OP_SSS_W, H4, H4, asub32)
RVVCALL(OPIVX2_RM, vasub_vx_d, OP_SSS_D, H8, H8, asub64)
GEN_VEXT_VX_RM(vasub_vx_b, 1, 1, clearb)
GEN_VEXT_VX_RM(vasub_vx_h, 2, 2, clearh)
GEN_VEXT_VX_RM(vasub_vx_w, 4, 4, clearl)
GEN_VEXT_VX_RM(vasub_vx_d, 8, 8, clearq)