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target/arm: Check access permission to ADDVL/ADDPL/RDVL

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These instructions do not trap when SVE is disabled in EL0,
causing them to be executed with wrong size information.

Backports commit 5de56742a3c91de3d646326bec43a989bba83ca4 from qemu
This commit is contained in:
Amir Charif 2019-03-19 05:42:50 -04:00 committed by Lioncash
parent 4dc3d59fd3
commit 2392d8b8ab
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 17 additions and 11 deletions
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28
qemu/target/arm/translate-sve.c
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@ -999,27 +999,33 @@ static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a)
static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a) static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; if (sve_access_check(s)) {
TCGv_i64 rd = cpu_reg_sp(s, a->rd); TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i64 rn = cpu_reg_sp(s, a->rn); TCGv_i64 rd = cpu_reg_sp(s, a->rd);
tcg_gen_addi_i64(tcg_ctx, rd, rn, a->imm * vec_full_reg_size(s)); TCGv_i64 rn = cpu_reg_sp(s, a->rn);
tcg_gen_addi_i64(tcg_ctx, rd, rn, a->imm * vec_full_reg_size(s));
}
return true; return true;
} }
static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; if (sve_access_check(s)) {
TCGv_i64 rd = cpu_reg_sp(s, a->rd); TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i64 rn = cpu_reg_sp(s, a->rn); TCGv_i64 rd = cpu_reg_sp(s, a->rd);
tcg_gen_addi_i64(tcg_ctx, rd, rn, a->imm * pred_full_reg_size(s)); TCGv_i64 rn = cpu_reg_sp(s, a->rn);
tcg_gen_addi_i64(tcg_ctx, rd, rn, a->imm * pred_full_reg_size(s));
}
return true; return true;
} }
static bool trans_RDVL(DisasContext *s, arg_RDVL *a) static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; if (sve_access_check(s)) {
TCGv_i64 reg = cpu_reg(s, a->rd); TCGContext *tcg_ctx = s->uc->tcg_ctx;
tcg_gen_movi_i64(tcg_ctx, reg, a->imm * vec_full_reg_size(s)); TCGv_i64 reg = cpu_reg(s, a->rd);
tcg_gen_movi_i64(tcg_ctx, reg, a->imm * vec_full_reg_size(s));
}
return true; return true;
} }