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target/arm: Export aa64_va_parameters to internals.h
We need to reuse this from helper-a64.c. Provide a stub definition for CONFIG_USER_ONLY. This matches the stub definitions that we removed for arm_regime_tbi{0,1} before. Backports commit bf0be433878935e824479e8ae890493e1fb646ed from qemu
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@ -3271,6 +3271,7 @@
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#define xscale_cp_reginfo xscale_cp_reginfo_aarch64
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#define xscale_cp_reginfo xscale_cp_reginfo_aarch64
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#define xscale_cpar_write xscale_cpar_write_aarch64
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#define xscale_cpar_write xscale_cpar_write_aarch64
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#define ARM64_REGS_STORAGE_SIZE ARM64_REGS_STORAGE_SIZE_aarch64
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#define ARM64_REGS_STORAGE_SIZE ARM64_REGS_STORAGE_SIZE_aarch64
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#define aa64_va_parameters aa64_va_parameters_aarch64
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#define aarch64_cpu_do_interrupt aarch64_cpu_do_interrupt_aarch64
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#define aarch64_cpu_do_interrupt aarch64_cpu_do_interrupt_aarch64
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#define aarch64_cpu_register_types aarch64_cpu_register_types_aarch64
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#define aarch64_cpu_register_types aarch64_cpu_register_types_aarch64
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#define aarch64_sve_change_el aarch64_sve_change_el_aarch64
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#define aarch64_sve_change_el aarch64_sve_change_el_aarch64
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@ -3271,6 +3271,7 @@
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#define xscale_cp_reginfo xscale_cp_reginfo_aarch64eb
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#define xscale_cp_reginfo xscale_cp_reginfo_aarch64eb
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#define xscale_cpar_write xscale_cpar_write_aarch64eb
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#define xscale_cpar_write xscale_cpar_write_aarch64eb
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#define ARM64_REGS_STORAGE_SIZE ARM64_REGS_STORAGE_SIZE_aarch64eb
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#define ARM64_REGS_STORAGE_SIZE ARM64_REGS_STORAGE_SIZE_aarch64eb
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#define aa64_va_parameters aa64_va_parameters_aarch64eb
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#define aarch64_cpu_do_interrupt aarch64_cpu_do_interrupt_aarch64eb
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#define aarch64_cpu_do_interrupt aarch64_cpu_do_interrupt_aarch64eb
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#define aarch64_cpu_register_types aarch64_cpu_register_types_aarch64eb
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#define aarch64_cpu_register_types aarch64_cpu_register_types_aarch64eb
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#define aarch64_sve_change_el aarch64_sve_change_el_aarch64eb
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#define aarch64_sve_change_el aarch64_sve_change_el_aarch64eb
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@ -3270,6 +3270,7 @@
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#define xpsr_write xpsr_write_arm
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#define xpsr_write xpsr_write_arm
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#define xscale_cp_reginfo xscale_cp_reginfo_arm
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#define xscale_cp_reginfo xscale_cp_reginfo_arm
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#define xscale_cpar_write xscale_cpar_write_arm
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#define xscale_cpar_write xscale_cpar_write_arm
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#define aa64_va_parameters aa64_va_parameters_arm
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#define aarch64_translator_ops aarch64_translator_ops_arm
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#define aarch64_translator_ops aarch64_translator_ops_arm
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#define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_arm
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#define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_arm
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#define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_arm
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#define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_arm
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@ -3270,6 +3270,7 @@
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#define xpsr_write xpsr_write_armeb
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#define xpsr_write xpsr_write_armeb
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#define xscale_cp_reginfo xscale_cp_reginfo_armeb
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#define xscale_cp_reginfo xscale_cp_reginfo_armeb
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#define xscale_cpar_write xscale_cpar_write_armeb
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#define xscale_cpar_write xscale_cpar_write_armeb
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#define aa64_va_parameters aa64_va_parameters_armeb
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#define aarch64_translator_ops aarch64_translator_ops_armeb
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#define aarch64_translator_ops aarch64_translator_ops_armeb
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#define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_armeb
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#define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_armeb
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#define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_armeb
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#define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_armeb
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@ -3279,6 +3279,7 @@ symbols = (
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)
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)
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arm_symbols = (
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arm_symbols = (
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'aa64_va_parameters',
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'aarch64_translator_ops',
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'aarch64_translator_ops',
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'arm_v7m_mmu_idx_for_secstate',
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'arm_v7m_mmu_idx_for_secstate',
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'arm_v7m_mmu_idx_for_secstate_and_priv',
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'arm_v7m_mmu_idx_for_secstate_and_priv',
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@ -3310,6 +3311,7 @@ arm_symbols = (
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aarch64_symbols = (
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aarch64_symbols = (
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'ARM64_REGS_STORAGE_SIZE',
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'ARM64_REGS_STORAGE_SIZE',
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'aa64_va_parameters',
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'aarch64_cpu_do_interrupt',
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'aarch64_cpu_do_interrupt',
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'aarch64_cpu_register_types',
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'aarch64_cpu_register_types',
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'aarch64_sve_change_el',
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'aarch64_sve_change_el',
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@ -8948,8 +8948,8 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
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return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint;
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return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint;
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}
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}
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static ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
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ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
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ARMMMUIdx mmu_idx, bool data)
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ARMMMUIdx mmu_idx, bool data)
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{
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{
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uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
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uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
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uint32_t el = regime_el(env, mmu_idx);
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uint32_t el = regime_el(env, mmu_idx);
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@ -958,4 +958,22 @@ typedef struct ARMVAParameters {
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bool using64k : 1;
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bool using64k : 1;
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} ARMVAParameters;
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} ARMVAParameters;
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#ifdef CONFIG_USER_ONLY
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static inline ARMVAParameters aa64_va_parameters(CPUARMState *env,
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uint64_t va,
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ARMMMUIdx mmu_idx, bool data)
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{
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ARMVAParameters result = {0};
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/* 48-bit address space */
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result.tsz = 16;
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/* We can't handle tagged addresses properly in user-only mode */
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result.tbi = false;
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return result;
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}
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#else
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ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
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ARMMMUIdx mmu_idx, bool data);
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#endif
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#endif
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#endif
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