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@ -206,6 +206,7 @@ class Uc(object):
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except: # _uc might be pulled from under our feet
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pass
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# emulate from @begin, and stop when reaching address @until
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def emu_start(self, begin, until, timeout=0, count=0):
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status = _uc.uc_emu_start(self._uch, begin, until, timeout, count)
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@ -74,7 +74,7 @@ typedef enum uc_x86_reg {
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UC_X86_REG_R14D, UC_X86_REG_R15D, UC_X86_REG_R8W, UC_X86_REG_R9W, UC_X86_REG_R10W,
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UC_X86_REG_R11W, UC_X86_REG_R12W, UC_X86_REG_R13W, UC_X86_REG_R14W, UC_X86_REG_R15W,
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UC_X86_REG_IDTR, UC_X86_REG_GDTR, UC_X86_REG_LDTR, UC_X86_REG_TR, UC_X86_REG_FPCW,
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UC_X86_REG_FPTAG,
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UC_X86_REG_FPTAG,
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UC_X86_REG_ENDING // <-- mark the end of the list of registers
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} uc_x86_reg;
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@ -152,7 +152,7 @@ int x86_reg_read(struct uc_struct *uc, unsigned int regid, void *value)
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case UC_X86_REG_FPSW:
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{
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uint16_t fpus = X86_CPU(uc, mycpu)->env.fpus;
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fpus = fpus & ~0x3800;
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fpus = fpus & ~0x3800;
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fpus |= ( X86_CPU(uc, mycpu)->env.fpstt & 0x7 ) << 11;
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*(uint16_t*) value = fpus;
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}
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@ -629,9 +629,8 @@ int x86_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
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break;
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case UC_X86_REG_FP0 ... UC_X86_REG_FP7:
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{
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//floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper);
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uint64_t mant = *(uint64_t*) value;
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uint16_t upper = *(uint16_t*) (value+sizeof(uint64_t));
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uint16_t upper = *(uint16_t*) (value + sizeof(uint64_t));
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X86_CPU(uc, mycpu)->env.fpregs[regid - UC_X86_REG_FP0].d = cpu_set_fp80(mant, upper);
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}
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break;
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@ -654,7 +653,8 @@ int x86_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
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fptag >>= 2;
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}
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}
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}
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break;
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}
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switch(uc->mode) {
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default:
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