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target/arm: Add support for MTE to SCTLR_ELx

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target/arm: Add support for MTE to HCR_EL2 and SCR_EL3

This does not attempt to rectify all of the res0 bits, but does
clear the mte bits when not enabled. Since there is no high-part
mapping of SCTLR, aa32 mode cannot write to these bits.

Backports commits f00faf130d5dcf64b04f71a95f14745845ca1014, and
8ddb300bf60a5f3d358dd6fbf81174f6c03c1d9f from qemu.
This commit is contained in:
Richard Henderson 2021-02-25 13:57:53 -05:00 committed by Lioncash
parent d81feac642
commit 2540911bdd
1 changed files with 17 additions and 6 deletions
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23
qemu/target/arm/helper.c
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@ -4417,6 +4417,22 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
{ {
ARMCPU *cpu = env_archcpu(env); ARMCPU *cpu = env_archcpu(env);
if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) {
/* M bit is RAZ/WI for PMSA with no MPU implemented */
value &= ~SCTLR_M;
}
/* ??? Lots of these bits are not implemented. */
if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) {
if (ri->opc1 == 6) { /* SCTLR_EL3 */
value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA);
} else {
value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF |
SCTLR_ATA0 | SCTLR_ATA);
}
}
if (raw_read(env, ri) == value) { if (raw_read(env, ri) == value) {
/* Skip the TLB flush if nothing actually changed; Linux likes /* Skip the TLB flush if nothing actually changed; Linux likes
* to do a lot of pointless SCTLR writes. * to do a lot of pointless SCTLR writes.
@ -4424,13 +4440,8 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
return; return;
} }
if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) {
/* M bit is RAZ/WI for PMSA with no MPU implemented */
value &= ~SCTLR_M;
}
raw_write(env, ri, value); raw_write(env, ri, value);
/* ??? Lots of these bits are not implemented. */
/* This may enable/disable the MMU, so do a TLB flush. */ /* This may enable/disable the MMU, so do a TLB flush. */
tlb_flush(CPU(cpu)); tlb_flush(CPU(cpu));
} }