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tcg-mips: Adjust calling conventions for mips64

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Backports commit 999b941633cabf2487d9bc77ce382b3fde3cd66d from qemu
This commit is contained in:
Jin Guojie 2018-03-01 12:53:38 -05:00 committed by Lioncash
parent 3de761976c
commit 25b4e11814
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 30 additions and 10 deletions
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19
qemu/tcg/mips/tcg-target.h
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@ -27,7 +27,14 @@
#ifndef MIPS_TCG_TARGET_H #ifndef MIPS_TCG_TARGET_H
#define MIPS_TCG_TARGET_H #define MIPS_TCG_TARGET_H
#define TCG_TARGET_REG_BITS 32 #if _MIPS_SIM == _ABIO32
# define TCG_TARGET_REG_BITS 32
#elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
# define TCG_TARGET_REG_BITS 64
#else
# error "Unknown ABI"
#endif
#define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_INSN_UNIT_SIZE 4
#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
#define TCG_TARGET_NB_REGS 32 #define TCG_TARGET_NB_REGS 32
@ -71,9 +78,13 @@ typedef enum {
} TCGReg; } TCGReg;
/* used for function call generation */ /* used for function call generation */
#define TCG_TARGET_STACK_ALIGN 8 #define TCG_TARGET_STACK_ALIGN 16
#define TCG_TARGET_CALL_STACK_OFFSET 16 #if _MIPS_SIM == _ABIO32
#define TCG_TARGET_CALL_ALIGN_ARGS 1 # define TCG_TARGET_CALL_STACK_OFFSET 16
#else
# define TCG_TARGET_CALL_STACK_OFFSET 0
#endif
#define TCG_TARGET_CALL_ALIGN_ARGS 1
/* MOVN/MOVZ instructions detection */ /* MOVN/MOVZ instructions detection */
#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \ #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \

21
qemu/tcg/mips/tcg-target.inc.c
View file

@ -91,10 +91,6 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_S8, TCG_REG_S8,
/* Call clobbered registers. */ /* Call clobbered registers. */
TCG_REG_T0,
TCG_REG_T1,
TCG_REG_T2,
TCG_REG_T3,
TCG_REG_T4, TCG_REG_T4,
TCG_REG_T5, TCG_REG_T5,
TCG_REG_T6, TCG_REG_T6,
@ -105,17 +101,27 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_V0, TCG_REG_V0,
/* Argument registers, opposite order of allocation. */ /* Argument registers, opposite order of allocation. */
TCG_REG_T3,
TCG_REG_T2,
TCG_REG_T1,
TCG_REG_T0,
TCG_REG_A3, TCG_REG_A3,
TCG_REG_A2, TCG_REG_A2,
TCG_REG_A1, TCG_REG_A1,
TCG_REG_A0, TCG_REG_A0,
}; };
static const TCGReg tcg_target_call_iarg_regs[4] = { static const TCGReg tcg_target_call_iarg_regs[] = {
TCG_REG_A0, TCG_REG_A0,
TCG_REG_A1, TCG_REG_A1,
TCG_REG_A2, TCG_REG_A2,
TCG_REG_A3 TCG_REG_A3,
#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
TCG_REG_T0,
TCG_REG_T1,
TCG_REG_T2,
TCG_REG_T3,
#endif
}; };
static const TCGReg tcg_target_call_oarg_regs[2] = { static const TCGReg tcg_target_call_oarg_regs[2] = {
@ -2443,6 +2449,9 @@ static void tcg_target_init(TCGContext *s)
{ {
tcg_target_detect_isa(); tcg_target_detect_isa();
tcg_regset_set(s->tcg_target_available_regs[TCG_TYPE_I32], 0xffffffff); tcg_regset_set(s->tcg_target_available_regs[TCG_TYPE_I32], 0xffffffff);
if (TCG_TARGET_REG_BITS == 64) {
tcg_regset_set(s->tcg_target_available_regs[TCG_TYPE_I64], 0xffffffff);
}
tcg_regset_set(s->tcg_target_call_clobber_regs, tcg_regset_set(s->tcg_target_call_clobber_regs,
(1 << TCG_REG_V0) | (1 << TCG_REG_V0) |
(1 << TCG_REG_V1) | (1 << TCG_REG_V1) |