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target/arm: Split out alle1_tlbmask

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No functional change, but unify code sequences.

Backports commit 90c19cdf1de440d7d9745cf255168999071b3a31 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 13:57:02 -04:00 committed by Lioncash
parent 6d4a7b84b5
commit 270d557a99
1 changed files with 24 additions and 60 deletions
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84
qemu/target/arm/helper.c
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@ -3749,34 +3749,32 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
tlb_flush_by_mmuidx(cs, mask); tlb_flush_by_mmuidx(cs, mask);
} }
static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, static int alle1_tlbmask(CPUARMState *env)
uint64_t value)
{ {
/* Note that the 'ALL' scope must invalidate both stage 1 and /*
* Note that the 'ALL' scope must invalidate both stage 1 and
* stage 2 translations, whereas most other scopes only invalidate * stage 2 translations, whereas most other scopes only invalidate
* stage 1 translations. * stage 1 translations.
*/ */
ARMCPU *cpu = env_archcpu(env);
CPUState *cs = CPU(cpu);
if (arm_is_secure_below_el3(env)) { if (arm_is_secure_below_el3(env)) {
tlb_flush_by_mmuidx(cs, return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
ARMMMUIdxBit_S1SE1 | } else if (arm_feature(env, ARM_FEATURE_EL2)) {
ARMMMUIdxBit_S1SE0); return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_S2NS;
} else { } else {
if (arm_feature(env, ARM_FEATURE_EL2)) { return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
tlb_flush_by_mmuidx(cs,
ARMMMUIdxBit_S12NSE1 |
ARMMMUIdxBit_S12NSE0 |
ARMMMUIdxBit_S2NS);
} else {
tlb_flush_by_mmuidx(cs,
ARMMMUIdxBit_S12NSE1 |
ARMMMUIdxBit_S12NSE0);
}
} }
} }
static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
CPUState *cs = env_cpu(env);
int mask = alle1_tlbmask(env);
tlb_flush_by_mmuidx(cs, mask);
}
static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
@ -3798,30 +3796,12 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
/* Note that the 'ALL' scope must invalidate both stage 1 and
* stage 2 translations, whereas most other scopes only invalidate
* stage 1 translations.
*/
// UNICORN: TODO: issue #642 // UNICORN: TODO: issue #642
#if 0 #if 0
bool sec = arm_is_secure_below_el3(env);
bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
int mask = alle1_tlbmask(env);
if (sec) { tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
tlb_flush_by_mmuidx_all_cpus_synced(cs,
ARMMMUIdxBit_S1SE1 |
ARMMMUIdxBit_S1SE0);
} else if (has_el2) {
tlb_flush_by_mmuidx_all_cpus_synced(cs,
ARMMMUIdxBit_S12NSE1 |
ARMMMUIdxBit_S12NSE0 |
ARMMMUIdxBit_S2NS);
} else {
tlb_flush_by_mmuidx_all_cpus_synced(cs,
ARMMMUIdxBit_S12NSE1 |
ARMMMUIdxBit_S12NSE0);
}
#endif #endif
} }
@ -3880,19 +3860,11 @@ static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
{ {
// UNICORN: TODO: issue #642 // UNICORN: TODO: issue #642
#if 0 #if 0
bool sec = arm_is_secure_below_el3(env); CPUState *cs = env_cpu(env);
CPUState *cs = env_cpu(env) int mask = vae1_tlbmask(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56); uint64_t pageaddr = sextract64(value << 12, 0, 56);
if (sec) { tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
ARMMMUIdxBit_S1SE1 |
ARMMMUIdxBit_S1SE0);
} else {
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
ARMMMUIdxBit_S12NSE1 |
ARMMMUIdxBit_S12NSE0);
}
#endif #endif
} }
@ -3904,8 +3876,8 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
* since we don't support flush-for-specific-ASID-only or * since we don't support flush-for-specific-ASID-only or
* flush-last-level-only. * flush-last-level-only.
*/ */
ARMCPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env);
CPUState *cs = CPU(cpu); int mask = vae1_tlbmask(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56); uint64_t pageaddr = sextract64(value << 12, 0, 56);
if (tlb_force_broadcast(env)) { if (tlb_force_broadcast(env)) {
@ -3913,15 +3885,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
return; return;
} }
if (arm_is_secure_below_el3(env)) { tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
tlb_flush_page_by_mmuidx(cs, pageaddr,
ARMMMUIdxBit_S1SE1 |
ARMMMUIdxBit_S1SE0);
} else {
tlb_flush_page_by_mmuidx(cs, pageaddr,
ARMMMUIdxBit_S12NSE1 |
ARMMMUIdxBit_S12NSE0);
}
} }
static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,