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fix register widths for MIPS64 reg_read/write (#775)
* fix register widths for MIPS64 reg_read/write * fix preprocessor typedef error for qemu/target-mips
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@ -18,6 +18,12 @@ const int MIPS_REGS_STORAGE_SIZE = offsetof(CPUMIPSState, tlb_table);
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#endif
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#endif
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#endif
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#endif
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#ifdef TARGET_MIPS64
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typedef uint64_t mipsreg_t;
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#else
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typedef uint32_t mipsreg_t;
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#endif
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static uint64_t mips_mem_redirect(uint64_t address)
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static uint64_t mips_mem_redirect(uint64_t address)
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{
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{
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// kseg0 range masks off high address bit
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// kseg0 range masks off high address bit
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@ -89,7 +95,7 @@ int mips_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int cou
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switch(regid) {
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switch(regid) {
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default: break;
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default: break;
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case UC_MIPS_REG_PC:
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case UC_MIPS_REG_PC:
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*(int32_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.PC;
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*(mipsreg_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.PC;
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break;
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break;
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}
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}
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}
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}
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@ -107,12 +113,12 @@ int mips_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals,
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unsigned int regid = regs[i];
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unsigned int regid = regs[i];
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const void *value = vals[i];
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const void *value = vals[i];
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if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31)
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if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31)
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MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - UC_MIPS_REG_0] = *(uint32_t *)value;
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MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - UC_MIPS_REG_0] = *(mipsreg_t *)value;
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else {
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else {
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switch(regid) {
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switch(regid) {
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default: break;
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default: break;
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case UC_MIPS_REG_PC:
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case UC_MIPS_REG_PC:
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MIPS_CPU(uc, mycpu)->env.active_tc.PC = *(uint32_t *)value;
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MIPS_CPU(uc, mycpu)->env.active_tc.PC = *(mipsreg_t *)value;
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// force to quit execution and flush TB
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// force to quit execution and flush TB
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uc->quit_request = true;
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uc->quit_request = true;
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uc_emu_stop(uc);
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uc_emu_stop(uc);
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