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target-arm: make DFSR banked
When EL3 is running in AArch32 (or ARMv7 with Security Extensions) DFSR has a secure and a non-secure instance. Backports commit 4a7e2d7315bd2ce28e49ccd0bde73eabdfd7437b from qemu
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@ -253,7 +253,15 @@ typedef struct CPUARMState {
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uint64_t ifsr32_el2;
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};
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};
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uint64_t esr_el[4];
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union {
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struct {
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uint64_t _unused_dfsr;
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uint64_t dfsr_ns;
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uint64_t hsr;
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uint64_t dfsr_s;
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};
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uint64_t esr_el[4];
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};
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uint32_t c6_region[8]; /* MPU base/size registers. */
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uint64_t far_el[4]; /* Fault address registers. */
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uint64_t par_el1; /* Translation result. */
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@ -1408,7 +1408,8 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static const ARMCPRegInfo vmsa_cp_reginfo[] = {
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{ "DFSR", 15,5,0, 0,0,0, 0,
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ARM_CP_NO_MIGRATE, PL1_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.esr_el[1]), {0, 0},
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ARM_CP_NO_MIGRATE, PL1_RW, 0, NULL, 0, 0,
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{ offsetoflow32(CPUARMState, cp15.dfsr_s), offsetoflow32(CPUARMState, cp15.dfsr_ns) },
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NULL,NULL,NULL,NULL,NULL, arm_cp_reset_ignore, },
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{ "IFSR", 15,5,0, 0,0,1, 0,
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0, PL1_RW, 0, NULL, 0, 0,
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@ -3837,11 +3838,11 @@ void arm_cpu_do_interrupt(CPUState *cs)
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offset = 4;
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break;
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case EXCP_DATA_ABORT:
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env->cp15.esr_el[1] = env->exception.fsr;
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A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
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env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32,
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env->exception.vaddress);
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qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
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(uint32_t)env->cp15.esr_el[1],
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env->exception.fsr,
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(uint32_t)env->exception.vaddress);
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new_mode = ARM_CPU_MODE_ABT;
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addr = 0x10;
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