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mips: Fix memleak

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This commit is contained in:
danghvu 2016-07-09 20:16:00 -05:00
parent 117a318188
commit 27e0699ef5
7 changed files with 37 additions and 3 deletions
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3
qemu/header_gen.py
View file

@ -4078,7 +4078,8 @@ mips_symbols = (
'mips_reg_read', 'mips_reg_read',
'mips_reg_write', 'mips_reg_write',
'mips_tcg_init', 'mips_tcg_init',
'mips_cpu_list' 'mips_cpu_list',
'mips_release'
) )
sparc_symbols = ( sparc_symbols = (

4
qemu/hw/mips/mips_r4k.c
View file

@ -35,8 +35,8 @@ static int mips_r4k_init(struct uc_struct *uc, MachineState *machine)
#endif #endif
} }
cpu = cpu_mips_init(uc, cpu_model); uc->cpu = (void*) cpu_mips_init(uc, cpu_model);
if (cpu == NULL) { if (uc->cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n"); fprintf(stderr, "Unable to find CPU definition\n");
return -1; return -1;
} }

1
qemu/mips.h
View file

@ -4070,4 +4070,5 @@
#define mips_reg_write mips_reg_write_mips #define mips_reg_write mips_reg_write_mips
#define mips_tcg_init mips_tcg_init_mips #define mips_tcg_init mips_tcg_init_mips
#define mips_cpu_list mips_cpu_list_mips #define mips_cpu_list mips_cpu_list_mips
#define mips_release mips_release_mips
#endif #endif

1
qemu/mips64.h
View file

@ -4070,4 +4070,5 @@
#define mips_reg_write mips_reg_write_mips64 #define mips_reg_write mips_reg_write_mips64
#define mips_tcg_init mips_tcg_init_mips64 #define mips_tcg_init mips_tcg_init_mips64
#define mips_cpu_list mips_cpu_list_mips64 #define mips_cpu_list mips_cpu_list_mips64
#define mips_release mips_release_mips64
#endif #endif

1
qemu/mips64el.h
View file

@ -4070,4 +4070,5 @@
#define mips_reg_write mips_reg_write_mips64el #define mips_reg_write mips_reg_write_mips64el
#define mips_tcg_init mips_tcg_init_mips64el #define mips_tcg_init mips_tcg_init_mips64el
#define mips_cpu_list mips_cpu_list_mips64el #define mips_cpu_list mips_cpu_list_mips64el
#define mips_release mips_release_mips64el
#endif #endif

1
qemu/mipsel.h
View file

@ -4070,4 +4070,5 @@
#define mips_reg_write mips_reg_write_mipsel #define mips_reg_write mips_reg_write_mipsel
#define mips_tcg_init mips_tcg_init_mipsel #define mips_tcg_init mips_tcg_init_mipsel
#define mips_cpu_list mips_cpu_list_mipsel #define mips_cpu_list mips_cpu_list_mipsel
#define mips_release mips_release_mipsel
#endif #endif

29
qemu/target-mips/unicorn.c
View file

@ -30,6 +30,34 @@ static void mips_set_pc(struct uc_struct *uc, uint64_t address)
((CPUMIPSState *)uc->current_cpu->env_ptr)->active_tc.PC = address; ((CPUMIPSState *)uc->current_cpu->env_ptr)->active_tc.PC = address;
} }
void mips_release(void *ctx);
void mips_release(void *ctx)
{
int i;
TCGContext *tcg_ctx = (TCGContext *) ctx;
release_common(ctx);
MIPSCPU* cpu = MIPS_CPU(tcg_ctx->uc, tcg_ctx->uc->cpu);
g_free(cpu->env.tlb);
g_free(cpu->env.mvp);
for (i = 0; i < MIPS_DSP_ACC; i++) {
g_free(tcg_ctx->cpu_HI[i]);
g_free(tcg_ctx->cpu_LO[i]);
}
for (i = 0; i < 32; i++) {
g_free(tcg_ctx->cpu_gpr[i]);
}
g_free(tcg_ctx->cpu_PC);
g_free(tcg_ctx->btarget);
g_free(tcg_ctx->bcond);
g_free(tcg_ctx->cpu_dspctrl);
g_free(tcg_ctx->tb_ctx.tbs);
}
void mips_reg_reset(struct uc_struct *uc) void mips_reg_reset(struct uc_struct *uc)
{ {
(void)uc; (void)uc;
@ -109,6 +137,7 @@ __attribute__ ((visibility ("default")))
uc->reg_read = mips_reg_read; uc->reg_read = mips_reg_read;
uc->reg_write = mips_reg_write; uc->reg_write = mips_reg_write;
uc->reg_reset = mips_reg_reset; uc->reg_reset = mips_reg_reset;
uc->release = mips_release;
uc->set_pc = mips_set_pc; uc->set_pc = mips_set_pc;
uc->mem_redirect = mips_mem_redirect; uc->mem_redirect = mips_mem_redirect;
uc_common_init(uc); uc_common_init(uc);