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target/arm: Convert Neon 2-reg-misc crypto operations to decodetree

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Convert the Neon-2-reg misc crypto ops (AESE, AESMC, SHA1H, SHA1SU1)
to decodetree.

Backports commit 0b30dd5b85e20aba259768cb7aaa952b3e319468 from qemu
This commit is contained in:
Peter Maydell 2021-02-25 12:32:37 -05:00 committed by Lioncash
parent 4354448f57
commit 27e74962e5
2 changed files with 48 additions and 51 deletions
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46
qemu/target/arm/translate-neon.inc.c
View file

@ -3422,7 +3422,7 @@ static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a)
return true;
}
fpst = get_fpstatus_ptr(s, true);
fpst = get_fpstatus_ptr(tcg_ctx, true);
ahp = get_ahp_flag(s);
tmp = neon_load_reg(s, a->vm, 0);
gen_helper_vfp_fcvt_f32_to_f16(tcg_ctx, tmp, tmp, fpst, ahp);
@ -3471,7 +3471,7 @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a)
return true;
}
fpst = get_fpstatus_ptr(s, true);
fpst = get_fpstatus_ptr(tcg_ctx, true);
ahp = get_ahp_flag(s);
tmp3 = tcg_temp_new_i32(tcg_ctx);
tmp = neon_load_reg(s, a->vm, 0);
@ -3550,3 +3550,45 @@ static bool trans_VMVN(DisasContext *s, arg_2misc *a)
}
return do_2misc_vec(s, a, tcg_gen_gvec_not);
}
#define WRAP_2M_3_OOL_FN(WRAPNAME, FUNC, DATA) \
static void WRAPNAME(TCGContext *s, unsigned vece, uint32_t rd_ofs, \
uint32_t rm_ofs, uint32_t oprsz, \
uint32_t maxsz) \
{ \
tcg_gen_gvec_3_ool(s, rd_ofs, rd_ofs, rm_ofs, oprsz, maxsz, \
DATA, FUNC); \
}
#define WRAP_2M_2_OOL_FN(WRAPNAME, FUNC, DATA) \
static void WRAPNAME(TCGContext *s, unsigned vece, uint32_t rd_ofs, \
uint32_t rm_ofs, uint32_t oprsz, \
uint32_t maxsz) \
{ \
tcg_gen_gvec_2_ool(s, rd_ofs, rm_ofs, oprsz, maxsz, DATA, FUNC); \
}
WRAP_2M_3_OOL_FN(gen_AESE, gen_helper_crypto_aese, 0)
WRAP_2M_3_OOL_FN(gen_AESD, gen_helper_crypto_aese, 1)
WRAP_2M_2_OOL_FN(gen_AESMC, gen_helper_crypto_aesmc, 0)
WRAP_2M_2_OOL_FN(gen_AESIMC, gen_helper_crypto_aesmc, 1)
WRAP_2M_2_OOL_FN(gen_SHA1H, gen_helper_crypto_sha1h, 0)
WRAP_2M_2_OOL_FN(gen_SHA1SU1, gen_helper_crypto_sha1su1, 0)
WRAP_2M_2_OOL_FN(gen_SHA256SU0, gen_helper_crypto_sha256su0, 0)
#define DO_2M_CRYPTO(INSN, FEATURE, SIZE) \
static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
{ \
if (!dc_isar_feature(FEATURE, s) || a->size != SIZE) { \
return false; \
} \
return do_2misc_vec(s, a, gen_##INSN); \
}
DO_2M_CRYPTO(AESE, aa32_aes, 0)
DO_2M_CRYPTO(AESD, aa32_aes, 0)
DO_2M_CRYPTO(AESMC, aa32_aes, 0)
DO_2M_CRYPTO(AESIMC, aa32_aes, 0)
DO_2M_CRYPTO(SHA1H, aa32_sha1, 2)
DO_2M_CRYPTO(SHA1SU1, aa32_sha1, 2)
DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2)

53
qemu/target/arm/translate.c
View file

@ -4960,7 +4960,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
TCGContext *tcg_ctx = s->uc->tcg_ctx;
int op;
int q;
int rd, rm, rd_ofs, rm_ofs;
int rd, rm;
int size;
int pass;
int u;
@ -4987,8 +4987,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
VFP_DREG_D(rd, insn);
VFP_DREG_M(rm, insn);
size = (insn >> 20) & 3;
rd_ofs = neon_reg_offset(rd, 0);
rm_ofs = neon_reg_offset(rm, 0);
if ((insn & (1 << 23)) == 0) {
/* Three register same length: handled by decodetree */
@ -5040,6 +5038,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
case NEON_2RM_VCLE0:
case NEON_2RM_VCGE0:
case NEON_2RM_VCLT0:
case NEON_2RM_AESE: case NEON_2RM_AESMC:
case NEON_2RM_SHA1H:
case NEON_2RM_SHA1SU1:
/* handled by decodetree */
return 1;
case NEON_2RM_VTRN:
@ -5055,52 +5056,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
goto elementwise;
}
break;
case NEON_2RM_AESE: case NEON_2RM_AESMC:
if (!dc_isar_feature(aa32_aes, s) || ((rm | rd) & 1)) {
return 1;
}
/*
* Bit 6 is the lowest opcode bit; it distinguishes
* between encryption (AESE/AESMC) and decryption
* (AESD/AESIMC).
*/
if (op == NEON_2RM_AESE) {
tcg_gen_gvec_3_ool(tcg_ctx, vfp_reg_offset(true, rd),
vfp_reg_offset(true, rd),
vfp_reg_offset(true, rm),
16, 16, extract32(insn, 6, 1),
gen_helper_crypto_aese);
} else {
tcg_gen_gvec_2_ool(tcg_ctx, vfp_reg_offset(true, rd),
vfp_reg_offset(true, rm),
16, 16, extract32(insn, 6, 1),
gen_helper_crypto_aesmc);
}
break;
case NEON_2RM_SHA1H:
if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) {
return 1;
}
tcg_gen_gvec_2_ool(tcg_ctx, rd_ofs, rm_ofs, 16, 16, 0,
gen_helper_crypto_sha1h);
break;
case NEON_2RM_SHA1SU1:
if ((rm | rd) & 1) {
return 1;
}
/* bit 6 (q): set -> SHA256SU0, cleared -> SHA1SU1 */
if (q) {
if (!dc_isar_feature(aa32_sha2, s)) {
return 1;
}
} else if (!dc_isar_feature(aa32_sha1, s)) {
return 1;
}
tcg_gen_gvec_2_ool(tcg_ctx, rd_ofs, rm_ofs, 16, 16, 0,
q ? gen_helper_crypto_sha256su0
: gen_helper_crypto_sha1su1);
break;
default:
elementwise: