mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-04-17 23:51:41 +00:00
target/riscv: Remove manual decoding of RV32/64M insn
Backports commit 1288701682d81b93f62e01cd87001dc90b30b881 from qemu
This commit is contained in:
Bastian Koppelmann
Lioncash
parent
b9eda7c464
commit
28daad082b
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@ -22,92 +22,102 @@
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static bool trans_mul(DisasContext *ctx, arg_mul *a)
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{
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REQUIRE_EXT(ctx, RVM);
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gen_arith(ctx, OPC_RISC_MUL, a->rd, a->rs1, a->rs2);
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return true;
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return trans_arith(ctx, a, &tcg_gen_mul_tl);
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}
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static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
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{
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REQUIRE_EXT(ctx, RVM);
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gen_arith(ctx, OPC_RISC_MULH, a->rd, a->rs1, a->rs2);
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv source1 = tcg_temp_new(tcg_ctx);
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TCGv source2 = tcg_temp_new(tcg_ctx);
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gen_get_gpr(ctx, source1, a->rs1);
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gen_get_gpr(ctx, source2, a->rs2);
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tcg_gen_muls2_tl(tcg_ctx, source2, source1, source1, source2);
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gen_set_gpr(ctx, a->rd, source1);
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tcg_temp_free(tcg_ctx, source1);
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tcg_temp_free(tcg_ctx, source2);
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return true;
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}
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static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
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{
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REQUIRE_EXT(ctx, RVM);
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gen_arith(ctx, OPC_RISC_MULHSU, a->rd, a->rs1, a->rs2);
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return true;
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return trans_arith(ctx, a, &gen_mulhsu);
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}
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static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
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{
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REQUIRE_EXT(ctx, RVM);
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gen_arith(ctx, OPC_RISC_MULHU, a->rd, a->rs1, a->rs2);
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv source1 = tcg_temp_new(tcg_ctx);
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TCGv source2 = tcg_temp_new(tcg_ctx);
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gen_get_gpr(ctx, source1, a->rs1);
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gen_get_gpr(ctx, source2, a->rs2);
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tcg_gen_mulu2_tl(tcg_ctx, source2, source1, source1, source2);
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gen_set_gpr(ctx, a->rd, source1);
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tcg_temp_free(tcg_ctx, source1);
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tcg_temp_free(tcg_ctx, source2);
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return true;
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}
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static bool trans_div(DisasContext *ctx, arg_div *a)
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{
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REQUIRE_EXT(ctx, RVM);
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gen_arith(ctx, OPC_RISC_DIV, a->rd, a->rs1, a->rs2);
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return true;
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return trans_arith(ctx, a, &gen_div);
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}
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static bool trans_divu(DisasContext *ctx, arg_divu *a)
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{
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REQUIRE_EXT(ctx, RVM);
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gen_arith(ctx, OPC_RISC_DIVU, a->rd, a->rs1, a->rs2);
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return true;
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return trans_arith(ctx, a, &gen_divu);
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}
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static bool trans_rem(DisasContext *ctx, arg_rem *a)
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{
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REQUIRE_EXT(ctx, RVM);
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gen_arith(ctx, OPC_RISC_REM, a->rd, a->rs1, a->rs2);
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return true;
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return trans_arith(ctx, a, &gen_rem);
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}
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static bool trans_remu(DisasContext *ctx, arg_remu *a)
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{
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REQUIRE_EXT(ctx, RVM);
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gen_arith(ctx, OPC_RISC_REMU, a->rd, a->rs1, a->rs2);
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return true;
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return trans_arith(ctx, a, &gen_remu);
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}
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#ifdef TARGET_RISCV64
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static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
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{
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REQUIRE_EXT(ctx, RVM);
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gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2);
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return true;
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return trans_arith(ctx, a, &gen_mulw);
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}
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static bool trans_divw(DisasContext *ctx, arg_divw *a)
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{
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REQUIRE_EXT(ctx, RVM);
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gen_arith(ctx, OPC_RISC_DIVW, a->rd, a->rs1, a->rs2);
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return true;
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return gen_arith_div_w(ctx, a, &gen_div);
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}
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static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
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{
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REQUIRE_EXT(ctx, RVM);
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gen_arith(ctx, OPC_RISC_DIVUW, a->rd, a->rs1, a->rs2);
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return true;
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return gen_arith_div_w(ctx, a, &gen_divu);
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}
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static bool trans_remw(DisasContext *ctx, arg_remw *a)
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{
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REQUIRE_EXT(ctx, RVM);
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gen_arith(ctx, OPC_RISC_REMW, a->rd, a->rs1, a->rs2);
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return true;
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return gen_arith_div_w(ctx, a, &gen_rem);
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}
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static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
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{
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REQUIRE_EXT(ctx, RVM);
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gen_arith(ctx, OPC_RISC_REMUW, a->rd, a->rs1, a->rs2);
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return true;
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return gen_arith_div_w(ctx, a, &gen_remu);
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}
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#endif
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@ -185,9 +185,8 @@ static inline void gen_set_gpr(const DisasContext *ctx, int reg_num_dst, TCGv t)
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}
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}
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static void gen_mulhsu(const DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2)
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static void gen_mulhsu(TCGContext *tcg_ctx, TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv rl = tcg_temp_new(tcg_ctx);
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TCGv rh = tcg_temp_new(tcg_ctx);
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@ -201,194 +200,112 @@ static void gen_mulhsu(const DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2)
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tcg_temp_free(tcg_ctx, rh);
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}
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static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
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int rs2)
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static void gen_div(TCGContext *tcg_ctx, TCGv ret, TCGv source1, TCGv source2)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv source1, source2, cond1, cond2, zeroreg, resultopt1;
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source1 = tcg_temp_new(tcg_ctx);
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source2 = tcg_temp_new(tcg_ctx);
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gen_get_gpr(ctx, source1, rs1);
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gen_get_gpr(ctx, source2, rs2);
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TCGv cond1, cond2, zeroreg, resultopt1;
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/*
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* Handle by altering args to tcg_gen_div to produce req'd results:
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* For overflow: want source1 in source1 and 1 in source2
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* For div by zero: want -1 in source1 and 1 in source2 -> -1 result
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*/
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cond1 = tcg_temp_new(tcg_ctx);
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cond2 = tcg_temp_new(tcg_ctx);
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zeroreg = tcg_const_tl(tcg_ctx, 0);
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resultopt1 = tcg_temp_new(tcg_ctx);
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switch (opc) {
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CASE_OP_32_64(OPC_RISC_MUL):
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if (!has_ext(ctx, RVM)) {
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goto do_illegal;
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}
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tcg_gen_mul_tl(tcg_ctx, source1, source1, source2);
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break;
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case OPC_RISC_MULH:
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if (!has_ext(ctx, RVM)) {
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goto do_illegal;
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}
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tcg_gen_muls2_tl(tcg_ctx, source2, source1, source1, source2);
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break;
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case OPC_RISC_MULHSU:
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if (!has_ext(ctx, RVM)) {
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goto do_illegal;
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}
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gen_mulhsu(ctx, source1, source1, source2);
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break;
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case OPC_RISC_MULHU:
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if (!has_ext(ctx, RVM)) {
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goto do_illegal;
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}
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tcg_gen_mulu2_tl(tcg_ctx, source2, source1, source1, source2);
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break;
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#if defined(TARGET_RISCV64)
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case OPC_RISC_DIVW:
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if (!has_ext(ctx, RVM)) {
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goto do_illegal;
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}
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tcg_gen_ext32s_tl(tcg_ctx, source1, source1);
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tcg_gen_ext32s_tl(tcg_ctx, source2, source2);
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/* fall through to DIV */
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#endif
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case OPC_RISC_DIV:
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if (!has_ext(ctx, RVM)) {
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goto do_illegal;
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}
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/* Handle by altering args to tcg_gen_div to produce req'd results:
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* For overflow: want source1 in source1 and 1 in source2
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* For div by zero: want -1 in source1 and 1 in source2 -> -1 result */
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cond1 = tcg_temp_new(tcg_ctx);
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cond2 = tcg_temp_new(tcg_ctx);
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zeroreg = tcg_const_tl(tcg_ctx, 0);
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resultopt1 = tcg_temp_new(tcg_ctx);
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tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)-1);
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tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
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tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source1,
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((target_ulong)1) << (TARGET_LONG_BITS - 1));
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tcg_gen_and_tl(tcg_ctx, cond1, cond1, cond2); /* cond1 = overflow */
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tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
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/* if div by zero, set source1 to -1, otherwise don't change */
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tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source1, cond2, zeroreg, source1,
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resultopt1);
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/* if overflow or div by zero, set source2 to 1, else don't change */
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tcg_gen_or_tl(tcg_ctx, cond1, cond1, cond2);
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tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)1);
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tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source2, cond1, zeroreg, source2,
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resultopt1);
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tcg_gen_div_tl(tcg_ctx, ret, source1, source2);
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tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)-1);
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tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
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tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source1,
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((target_ulong)1) << (TARGET_LONG_BITS - 1));
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tcg_gen_and_tl(tcg_ctx, cond1, cond1, cond2); /* cond1 = overflow */
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tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
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/* if div by zero, set source1 to -1, otherwise don't change */
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tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source1, cond2, zeroreg, source1,
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resultopt1);
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/* if overflow or div by zero, set source2 to 1, else don't change */
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tcg_gen_or_tl(tcg_ctx, cond1, cond1, cond2);
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tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)1);
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tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source2, cond1, zeroreg, source2,
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resultopt1);
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tcg_gen_div_tl(tcg_ctx, source1, source1, source2);
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tcg_temp_free(tcg_ctx, cond1);
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tcg_temp_free(tcg_ctx, cond2);
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tcg_temp_free(tcg_ctx, zeroreg);
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tcg_temp_free(tcg_ctx, resultopt1);
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}
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tcg_temp_free(tcg_ctx, cond1);
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tcg_temp_free(tcg_ctx, cond2);
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tcg_temp_free(tcg_ctx, zeroreg);
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tcg_temp_free(tcg_ctx, resultopt1);
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break;
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#if defined(TARGET_RISCV64)
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case OPC_RISC_DIVUW:
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if (!has_ext(ctx, RVM)) {
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goto do_illegal;
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}
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tcg_gen_ext32u_tl(tcg_ctx, source1, source1);
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tcg_gen_ext32u_tl(tcg_ctx, source2, source2);
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/* fall through to DIVU */
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#endif
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case OPC_RISC_DIVU:
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if (!has_ext(ctx, RVM)) {
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goto do_illegal;
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}
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cond1 = tcg_temp_new(tcg_ctx);
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zeroreg = tcg_const_tl(tcg_ctx, 0);
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resultopt1 = tcg_temp_new(tcg_ctx);
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static void gen_divu(TCGContext *tcg_ctx, TCGv ret, TCGv source1, TCGv source2)
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{
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TCGv cond1, zeroreg, resultopt1;
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cond1 = tcg_temp_new(tcg_ctx);
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tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source2, 0);
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tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)-1);
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tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source1, cond1, zeroreg, source1,
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resultopt1);
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tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)1);
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tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source2, cond1, zeroreg, source2,
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resultopt1);
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tcg_gen_divu_tl(tcg_ctx, source1, source1, source2);
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zeroreg = tcg_const_tl(tcg_ctx, 0);
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resultopt1 = tcg_temp_new(tcg_ctx);
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tcg_temp_free(tcg_ctx, cond1);
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tcg_temp_free(tcg_ctx, zeroreg);
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tcg_temp_free(tcg_ctx, resultopt1);
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break;
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#if defined(TARGET_RISCV64)
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case OPC_RISC_REMW:
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if (!has_ext(ctx, RVM)) {
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goto do_illegal;
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}
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tcg_gen_ext32s_tl(tcg_ctx, source1, source1);
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tcg_gen_ext32s_tl(tcg_ctx, source2, source2);
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/* fall through to REM */
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#endif
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case OPC_RISC_REM:
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if (!has_ext(ctx, RVM)) {
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goto do_illegal;
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}
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cond1 = tcg_temp_new(tcg_ctx);
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cond2 = tcg_temp_new(tcg_ctx);
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zeroreg = tcg_const_tl(tcg_ctx, 0);
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resultopt1 = tcg_temp_new(tcg_ctx);
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tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source2, 0);
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tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)-1);
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tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source1, cond1, zeroreg, source1,
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resultopt1);
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tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)1);
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tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source2, cond1, zeroreg, source2,
|
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resultopt1);
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tcg_gen_divu_tl(tcg_ctx, ret, source1, source2);
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tcg_gen_movi_tl(tcg_ctx, resultopt1, 1L);
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tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond2, source2, (target_ulong)-1);
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tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source1,
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(target_ulong)1 << (TARGET_LONG_BITS - 1));
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tcg_gen_and_tl(tcg_ctx, cond2, cond1, cond2); /* cond1 = overflow */
|
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tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
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/* if overflow or div by zero, set source2 to 1, else don't change */
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tcg_gen_or_tl(tcg_ctx, cond2, cond1, cond2);
|
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tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source2, cond2, zeroreg, source2,
|
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resultopt1);
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tcg_gen_rem_tl(tcg_ctx, resultopt1, source1, source2);
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/* if div by zero, just return the original dividend */
|
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tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source1, cond1, zeroreg, resultopt1,
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source1);
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tcg_temp_free(tcg_ctx, cond1);
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tcg_temp_free(tcg_ctx, zeroreg);
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tcg_temp_free(tcg_ctx, resultopt1);
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}
|
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|
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tcg_temp_free(tcg_ctx, cond1);
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tcg_temp_free(tcg_ctx, cond2);
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tcg_temp_free(tcg_ctx, zeroreg);
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tcg_temp_free(tcg_ctx, resultopt1);
|
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break;
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#if defined(TARGET_RISCV64)
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case OPC_RISC_REMUW:
|
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if (!has_ext(ctx, RVM)) {
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goto do_illegal;
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}
|
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tcg_gen_ext32u_tl(tcg_ctx, source1, source1);
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tcg_gen_ext32u_tl(tcg_ctx, source2, source2);
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/* fall through to REMU */
|
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#endif
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case OPC_RISC_REMU:
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if (!has_ext(ctx, RVM)) {
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goto do_illegal;
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}
|
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cond1 = tcg_temp_new(tcg_ctx);
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zeroreg = tcg_const_tl(tcg_ctx, 0);
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resultopt1 = tcg_temp_new(tcg_ctx);
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static void gen_rem(TCGContext *tcg_ctx, TCGv ret, TCGv source1, TCGv source2)
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{
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TCGv cond1, cond2, zeroreg, resultopt1;
|
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|
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tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)1);
|
||||
tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source2, 0);
|
||||
tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source2, cond1, zeroreg, source2,
|
||||
resultopt1);
|
||||
tcg_gen_remu_tl(tcg_ctx, resultopt1, source1, source2);
|
||||
/* if div by zero, just return the original dividend */
|
||||
tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source1, cond1, zeroreg, resultopt1,
|
||||
source1);
|
||||
cond1 = tcg_temp_new(tcg_ctx);
|
||||
cond2 = tcg_temp_new(tcg_ctx);
|
||||
zeroreg = tcg_const_tl(tcg_ctx, 0);
|
||||
resultopt1 = tcg_temp_new(tcg_ctx);
|
||||
|
||||
tcg_temp_free(tcg_ctx, cond1);
|
||||
tcg_temp_free(tcg_ctx, zeroreg);
|
||||
tcg_temp_free(tcg_ctx, resultopt1);
|
||||
break;
|
||||
do_illegal:
|
||||
default:
|
||||
gen_exception_illegal(ctx);
|
||||
return;
|
||||
}
|
||||
tcg_gen_movi_tl(tcg_ctx, resultopt1, 1L);
|
||||
tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond2, source2, (target_ulong)-1);
|
||||
tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source1,
|
||||
(target_ulong)1 << (TARGET_LONG_BITS - 1));
|
||||
tcg_gen_and_tl(tcg_ctx, cond2, cond1, cond2); /* cond1 = overflow */
|
||||
tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
|
||||
/* if overflow or div by zero, set source2 to 1, else don't change */
|
||||
tcg_gen_or_tl(tcg_ctx, cond2, cond1, cond2);
|
||||
tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source2, cond2, zeroreg, source2,
|
||||
resultopt1);
|
||||
tcg_gen_rem_tl(tcg_ctx, resultopt1, source1, source2);
|
||||
/* if div by zero, just return the original dividend */
|
||||
tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
|
||||
source1);
|
||||
|
||||
if (opc & 0x8) { /* sign extend for W instructions */
|
||||
tcg_gen_ext32s_tl(tcg_ctx, source1, source1);
|
||||
}
|
||||
tcg_temp_free(tcg_ctx, cond1);
|
||||
tcg_temp_free(tcg_ctx, cond2);
|
||||
tcg_temp_free(tcg_ctx, zeroreg);
|
||||
tcg_temp_free(tcg_ctx, resultopt1);
|
||||
}
|
||||
|
||||
gen_set_gpr(ctx, rd, source1);
|
||||
tcg_temp_free(tcg_ctx, source1);
|
||||
tcg_temp_free(tcg_ctx, source2);
|
||||
static void gen_remu(TCGContext *tcg_ctx, TCGv ret, TCGv source1, TCGv source2)
|
||||
{
|
||||
TCGv cond1, zeroreg, resultopt1;
|
||||
cond1 = tcg_temp_new(tcg_ctx);
|
||||
zeroreg = tcg_const_tl(tcg_ctx, 0);
|
||||
resultopt1 = tcg_temp_new(tcg_ctx);
|
||||
|
||||
tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)1);
|
||||
tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source2, 0);
|
||||
tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source2, cond1, zeroreg, source2,
|
||||
resultopt1);
|
||||
tcg_gen_remu_tl(tcg_ctx, resultopt1, source1, source2);
|
||||
/* if div by zero, just return the original dividend */
|
||||
tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
|
||||
source1);
|
||||
|
||||
tcg_temp_free(tcg_ctx, cond1);
|
||||
tcg_temp_free(tcg_ctx, zeroreg);
|
||||
tcg_temp_free(tcg_ctx, resultopt1);
|
||||
}
|
||||
|
||||
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
|
||||
|
|
@ -704,6 +621,34 @@ static void gen_subw(TCGContext *tcg_ctx, TCGv ret, TCGv arg1, TCGv arg2)
|
|||
tcg_gen_sub_tl(tcg_ctx, ret, arg1, arg2);
|
||||
tcg_gen_ext32s_tl(tcg_ctx, ret, ret);
|
||||
}
|
||||
|
||||
static void gen_mulw(TCGContext *tcg_ctx, TCGv ret, TCGv arg1, TCGv arg2)
|
||||
{
|
||||
tcg_gen_mul_tl(tcg_ctx, ret, arg1, arg2);
|
||||
tcg_gen_ext32s_tl(tcg_ctx, ret, ret);
|
||||
}
|
||||
|
||||
static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
|
||||
void(*func)(TCGContext *, TCGv, TCGv, TCGv))
|
||||
{
|
||||
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
|
||||
TCGv source1, source2;
|
||||
source1 = tcg_temp_new(tcg_ctx);
|
||||
source2 = tcg_temp_new(tcg_ctx);
|
||||
|
||||
gen_get_gpr(ctx, source1, a->rs1);
|
||||
gen_get_gpr(ctx, source2, a->rs2);
|
||||
tcg_gen_ext32s_tl(tcg_ctx, source1, source1);
|
||||
tcg_gen_ext32s_tl(tcg_ctx, source2, source2);
|
||||
|
||||
(*func)(tcg_ctx, source1, source1, source2);
|
||||
|
||||
tcg_gen_ext32s_tl(tcg_ctx, source1, source1);
|
||||
gen_set_gpr(ctx, a->rd, source1);
|
||||
tcg_temp_free(tcg_ctx, source1);
|
||||
tcg_temp_free(tcg_ctx, source2);
|
||||
return true;
|
||||
}
|
||||
#endif
|
||||
|
||||
static bool trans_arith(DisasContext *ctx, arg_r *a,
|
||||
|
|
|
|||
Loading…
Reference in a new issue