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target-m68k: define operand sizes

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Backports commit 7ef25cdd6cee4fa468d6cb913fa064a6689faf7d from qemu
This commit is contained in:
Laurent Vivier 2018-02-27 08:35:11 -05:00 committed by Lioncash
parent 2653165c63
commit 292fc83c86
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 24 additions and 32 deletions
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8
qemu/target-m68k/cpu.h
View file

@ -32,6 +32,14 @@
#include "fpu/softfloat.h"
#define OS_BYTE 0
#define OS_WORD 1
#define OS_LONG 2
#define OS_SINGLE 3
#define OS_DOUBLE 4
#define OS_EXTENDED 5
#define OS_PACKED 6
#define MAX_QREGS 32
#define EXCP_ACCESS 2 /* Access (MMU) error. */

48
qemu/target-m68k/translate.c
View file

@ -124,12 +124,6 @@ typedef struct DisasContext {
#define IS_USER(s) s->user
#endif
#define OS_BYTE 0
#define OS_WORD 1
#define OS_LONG 2
#define OS_SINGLE 4
#define OS_DOUBLE 5
typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
#ifdef DEBUG_DISPATCH
@ -429,6 +423,8 @@ static inline int opsize_bytes(int opsize)
case OS_LONG: return 4;
case OS_SINGLE: return 4;
case OS_DOUBLE: return 8;
case OS_EXTENDED: return 12;
case OS_PACKED: return 12;
default:
g_assert_not_reached();
return 0;
@ -437,6 +433,18 @@ static inline int opsize_bytes(int opsize)
return 0;
}
static inline int insn_opsize(int insn)
{
switch ((insn >> 6) & 3) {
case 0: return OS_BYTE;
case 1: return OS_WORD;
case 2: return OS_LONG;
default:
g_assert_not_reached();
return 0;
}
}
/* Assign value to a register. If the width is less than the register width
only the low part of the register is set. */
static void gen_partset_reg(DisasContext *s, int opsize, TCGv reg, TCGv val)
@ -1338,19 +1346,7 @@ DISAS_INSN(clr)
TCGContext *tcg_ctx = s->uc->tcg_ctx;
int opsize;
switch ((insn >> 6) & 3) {
case 0: /* clr.b */
opsize = OS_BYTE;
break;
case 1: /* clr.w */
opsize = OS_WORD;
break;
case 2: /* clr.l */
opsize = OS_LONG;
break;
default:
abort();
}
opsize = insn_opsize(insn);
DEST_EA(env, insn, opsize, tcg_const_i32(tcg_ctx, 0), NULL);
gen_logic_cc(s, tcg_const_i32(tcg_ctx, 0));
}
@ -1504,19 +1500,7 @@ DISAS_INSN(tst)
int opsize;
TCGv tmp;
switch ((insn >> 6) & 3) {
case 0: /* tst.b */
opsize = OS_BYTE;
break;
case 1: /* tst.w */
opsize = OS_WORD;
break;
case 2: /* tst.l */
opsize = OS_LONG;
break;
default:
abort();
}
opsize = insn_opsize(insn);
SRC_EA(env, tmp, opsize, 1, NULL);
gen_logic_cc(s, tmp);
}