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target/riscv: Add the HSTATUS register masks

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Backports commit d28b15a4d3b1e000ec7bf9090fe870cbc5f1eb2c from qemu
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Alistair Francis 2019-05-28 19:18:24 -04:00 committed by Lioncash
parent 2e6d11ee47
commit 294297b646
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1 changed files with 18 additions and 0 deletions
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18
qemu/target/riscv/cpu_bits.h
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@ -382,6 +382,24 @@
#define SSTATUS_SD SSTATUS64_SD
#endif
/* hstatus CSR bits */
#define HSTATUS_SPRV 0x00000001
#define HSTATUS_STL 0x00000040
#define HSTATUS_SPV 0x00000080
#define HSTATUS_SP2P 0x00000100
#define HSTATUS_SP2V 0x00000200
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTSR 0x00400000
#define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
#if defined(TARGET_RISCV32)
#define HSTATUS_WPRI HSTATUS32_WPRI
#elif defined(TARGET_RISCV64)
#define HSTATUS_WPRI HSTATUS64_WPRI
#endif
/* Privilege modes */
#define PRV_U 0
#define PRV_S 1