yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-01-09 09:25:39 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge remote-tracking branch 'upstream/master'

Browse source
This commit is contained in:
Chris Eagle 2015-08-24 00:50:59 -07:00
parent dffdf8d3f7 783b68c85b
commit 2998c125de
57 changed files with 5230 additions and 4965 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
CREDITS.TXT
View file

@ -32,7 +32,11 @@ Tim "diff" Strazzere
WanderingGlitch of the Zero Day Initiative WanderingGlitch of the Zero Day Initiative
Sascha Schirra Sascha Schirra
François Serman François Serman
Sean Heelan
Luke Burnett
Parker Thompson
Daniel Godas-Lopez
Antonio "s4tan" Parata
Contributors (in no particular order) Contributors (in no particular order)
===================================== =====================================

7
Makefile
View file

@ -287,6 +287,13 @@ header: FORCE
$(shell python qemu/header_gen.py $(var) > qemu/$(var).h;)) $(shell python qemu/header_gen.py $(var) > qemu/$(var).h;))
@echo "Generated headers for $(TARGETS)." @echo "Generated headers for $(TARGETS)."
uninstall:
rm -rf $(INCDIR)/$(LIBNAME)
rm -f $(LIBDIR)/lib$(LIBNAME).*
rm -f $(PKGCFGDIR)/$(LIBNAME).pc
clean: clean:
$(MAKE) -C qemu clean $(MAKE) -C qemu clean
rm -rf *.d *.o rm -rf *.d *.o

4
bindings/const_generator.py
View file

@ -50,7 +50,7 @@ def gen(lang):
if line == '' or line.startswith('//'): if line == '' or line.startswith('//'):
continue continue
if not line.startswith(prefix.upper()): if not line.startswith("UC_" + prefix.upper()):
continue continue
tmp = line.strip().split(',') tmp = line.strip().split(',')
@ -59,7 +59,7 @@ def gen(lang):
if not t or t.startswith('//'): continue if not t or t.startswith('//'): continue
f = re.split('\s+', t) f = re.split('\s+', t)
if f[0].startswith(prefix.upper()): if f[0].startswith("UC_" + prefix.upper()):
if len(f) > 1 and f[1] not in '//=': if len(f) > 1 and f[1] not in '//=':
print("Error: Unable to convert %s" % f) print("Error: Unable to convert %s" % f)
continue continue

14
bindings/python/sample_arm.py
View file

@ -38,9 +38,9 @@ def test_arm():
mu.mem_write(ADDRESS, ARM_CODE) mu.mem_write(ADDRESS, ARM_CODE)
# initialize machine registers # initialize machine registers
mu.reg_write(ARM_REG_R0, 0x1234) mu.reg_write(UC_ARM_REG_R0, 0x1234)
mu.reg_write(ARM_REG_R2, 0x6789) mu.reg_write(UC_ARM_REG_R2, 0x6789)
mu.reg_write(ARM_REG_R3, 0x3333) mu.reg_write(UC_ARM_REG_R3, 0x3333)
# tracing all basic blocks with customized callback # tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block) mu.hook_add(UC_HOOK_BLOCK, hook_block)
@ -54,8 +54,8 @@ def test_arm():
# now print out some registers # now print out some registers
print(">>> Emulation done. Below is the CPU context") print(">>> Emulation done. Below is the CPU context")
r0 = mu.reg_read(ARM_REG_R0) r0 = mu.reg_read(UC_ARM_REG_R0)
r1 = mu.reg_read(ARM_REG_R1) r1 = mu.reg_read(UC_ARM_REG_R1)
print(">>> R0 = 0x%x" %r0) print(">>> R0 = 0x%x" %r0)
print(">>> R1 = 0x%x" %r1) print(">>> R1 = 0x%x" %r1)
@ -76,7 +76,7 @@ def test_thumb():
mu.mem_write(ADDRESS, THUMB_CODE) mu.mem_write(ADDRESS, THUMB_CODE)
# initialize machine registers # initialize machine registers
mu.reg_write(ARM_REG_SP, 0x1234) mu.reg_write(UC_ARM_REG_SP, 0x1234)
# tracing all basic blocks with customized callback # tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block) mu.hook_add(UC_HOOK_BLOCK, hook_block)
@ -90,7 +90,7 @@ def test_thumb():
# now print out some registers # now print out some registers
print(">>> Emulation done. Below is the CPU context") print(">>> Emulation done. Below is the CPU context")
sp = mu.reg_read(ARM_REG_SP) sp = mu.reg_read(UC_ARM_REG_SP)
print(">>> SP = 0x%x" %sp) print(">>> SP = 0x%x" %sp)
except UcError as e: except UcError as e:

12
bindings/python/sample_arm64.py
View file

@ -38,9 +38,9 @@ def test_arm64():
mu.mem_write(ADDRESS, ARM64_CODE) mu.mem_write(ADDRESS, ARM64_CODE)
# initialize machine registers # initialize machine registers
mu.reg_write(ARM64_REG_X11, 0x1234) mu.reg_write(UC_ARM64_REG_X11, 0x1234)
mu.reg_write(ARM64_REG_X13, 0x6789) mu.reg_write(UC_ARM64_REG_X13, 0x6789)
mu.reg_write(ARM64_REG_X15, 0x3333) mu.reg_write(UC_ARM64_REG_X15, 0x3333)
# tracing all basic blocks with customized callback # tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block) mu.hook_add(UC_HOOK_BLOCK, hook_block)
@ -54,9 +54,9 @@ def test_arm64():
# now print out some registers # now print out some registers
print(">>> Emulation done. Below is the CPU context") print(">>> Emulation done. Below is the CPU context")
x11 = mu.reg_read(ARM64_REG_X11) x11 = mu.reg_read(UC_ARM64_REG_X11)
x13 = mu.reg_read(ARM64_REG_X13) x13 = mu.reg_read(UC_ARM64_REG_X13)
x15 = mu.reg_read(ARM64_REG_X15) x15 = mu.reg_read(UC_ARM64_REG_X15)
print(">>> X11 = 0x%x" %x11) print(">>> X11 = 0x%x" %x11)
except UcError as e: except UcError as e:

4
bindings/python/sample_m68k.py
View file

@ -37,7 +37,7 @@ def test_m68k():
mu.mem_write(ADDRESS, M68K_CODE) mu.mem_write(ADDRESS, M68K_CODE)
# initialize machine registers # initialize machine registers
mu.reg_write(M68K_REG_D3, 0x1234) mu.reg_write(UC_M68K_REG_D3, 0x1234)
# tracing all basic blocks with customized callback # tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block) mu.hook_add(UC_HOOK_BLOCK, hook_block)
@ -51,7 +51,7 @@ def test_m68k():
# now print out some registers # now print out some registers
print(">>> Emulation done. Below is the CPU context") print(">>> Emulation done. Below is the CPU context")
d3 = mu.reg_read(M68K_REG_D3) d3 = mu.reg_read(UC_M68K_REG_D3)
print(">>> D3 = 0x%x" %d3) print(">>> D3 = 0x%x" %d3)
except UcError as e: except UcError as e:

8
bindings/python/sample_mips.py
View file

@ -39,7 +39,7 @@ def test_mips_eb():
mu.mem_write(ADDRESS, MIPS_CODE_EB) mu.mem_write(ADDRESS, MIPS_CODE_EB)
# initialize machine registers # initialize machine registers
mu.reg_write(MIPS_REG_1, 0x6789) mu.reg_write(UC_MIPS_REG_1, 0x6789)
# tracing all basic blocks with customized callback # tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block) mu.hook_add(UC_HOOK_BLOCK, hook_block)
@ -53,7 +53,7 @@ def test_mips_eb():
# now print out some registers # now print out some registers
print(">>> Emulation done. Below is the CPU context") print(">>> Emulation done. Below is the CPU context")
r1 = mu.reg_read(MIPS_REG_1) r1 = mu.reg_read(UC_MIPS_REG_1)
print(">>> r1 = 0x%x" %r1) print(">>> r1 = 0x%x" %r1)
except UcError as e: except UcError as e:
@ -74,7 +74,7 @@ def test_mips_el():
mu.mem_write(ADDRESS, MIPS_CODE_EL) mu.mem_write(ADDRESS, MIPS_CODE_EL)
# initialize machine registers # initialize machine registers
mu.reg_write(MIPS_REG_1, 0x6789) mu.reg_write(UC_MIPS_REG_1, 0x6789)
# tracing all basic blocks with customized callback # tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block) mu.hook_add(UC_HOOK_BLOCK, hook_block)
@ -88,7 +88,7 @@ def test_mips_el():
# now print out some registers # now print out some registers
print(">>> Emulation done. Below is the CPU context") print(">>> Emulation done. Below is the CPU context")
r1 = mu.reg_read(MIPS_REG_1) r1 = mu.reg_read(UC_MIPS_REG_1)
print(">>> r1 = 0x%x" %r1) print(">>> r1 = 0x%x" %r1)
except UcError as e: except UcError as e:

20
bindings/python/sample_network_auditing.py
View file

@ -173,11 +173,11 @@ def hook_intr(uc, intno, user_data):
if intno != 0x80: if intno != 0x80:
return return
eax = uc.reg_read(X86_REG_EAX) eax = uc.reg_read(UC_X86_REG_EAX)
ebx = uc.reg_read(X86_REG_EBX) ebx = uc.reg_read(UC_X86_REG_EBX)
ecx = uc.reg_read(X86_REG_ECX) ecx = uc.reg_read(UC_X86_REG_ECX)
edx = uc.reg_read(X86_REG_EDX) edx = uc.reg_read(UC_X86_REG_EDX)
eip = uc.reg_read(X86_REG_EIP) eip = uc.reg_read(UC_X86_REG_EIP)
# print(">>> INTERRUPT %d" % eax) # print(">>> INTERRUPT %d" % eax)
@ -217,7 +217,7 @@ def hook_intr(uc, intno, user_data):
filename = uc.mem_read(filename_addr, FILENAME_MAX_LEN) filename = uc.mem_read(filename_addr, FILENAME_MAX_LEN)
dummy_fd = id_gen.next() dummy_fd = id_gen.next()
uc.reg_write(X86_REG_EAX, dummy_fd) uc.reg_write(UC_X86_REG_EAX, dummy_fd)
msg = "open file (filename=%s flags=%d mode=%d) with fd(%d)" % (bytearray_to_string(filename), flags, mode, dummy_fd) msg = "open file (filename=%s flags=%d mode=%d) with fd(%d)" % (bytearray_to_string(filename), flags, mode, dummy_fd)
@ -234,8 +234,8 @@ def hook_intr(uc, intno, user_data):
print(">>> SYS_DUP2 oldfd=%d newfd=%d" % (ebx, ecx)) print(">>> SYS_DUP2 oldfd=%d newfd=%d" % (ebx, ecx))
elif eax == 102: # sys_socketcall elif eax == 102: # sys_socketcall
# ref: http://www.skyfree.org/linux/kernel_network/socket.html # ref: http://www.skyfree.org/linux/kernel_network/socket.html
call = uc.reg_read(X86_REG_EBX) call = uc.reg_read(UC_X86_REG_EBX)
args = uc.reg_read(X86_REG_ECX) args = uc.reg_read(UC_X86_REG_ECX)
buf = uc.mem_read(args, SOCKETCALL_MAX_ARGS*SIZE_REG) buf = uc.mem_read(args, SOCKETCALL_MAX_ARGS*SIZE_REG)
args = struct.unpack("<" + "I"*SOCKETCALL_MAX_ARGS, buf) args = struct.unpack("<" + "I"*SOCKETCALL_MAX_ARGS, buf)
@ -249,7 +249,7 @@ def hook_intr(uc, intno, user_data):
protocol = args[2] protocol = args[2]
dummy_fd = id_gen.next() dummy_fd = id_gen.next()
uc.reg_write(X86_REG_EAX, dummy_fd) uc.reg_write(UC_X86_REG_EAX, dummy_fd)
if family == 2: # AF_INET if family == 2: # AF_INET
@ -353,7 +353,7 @@ def test_i386(code):
mu.mem_write(ADDRESS, code) mu.mem_write(ADDRESS, code)
# initialize stack # initialize stack
mu.reg_write(X86_REG_ESP, ADDRESS + 0x200000) mu.reg_write(UC_X86_REG_ESP, ADDRESS + 0x200000)
# tracing all instructions with customized callback # tracing all instructions with customized callback
# mu.hook_add(UC_HOOK_CODE, hook_code) # mu.hook_add(UC_HOOK_CODE, hook_code)

8
bindings/python/sample_sparc.py
View file

@ -37,9 +37,9 @@ def test_sparc():
mu.mem_write(ADDRESS, SPARC_CODE) mu.mem_write(ADDRESS, SPARC_CODE)
# initialize machine registers # initialize machine registers
mu.reg_write(SPARC_REG_G1, 0x1230) mu.reg_write(UC_SPARC_REG_G1, 0x1230)
mu.reg_write(SPARC_REG_G2, 0x6789) mu.reg_write(UC_SPARC_REG_G2, 0x6789)
mu.reg_write(SPARC_REG_G3, 0x5555) mu.reg_write(UC_SPARC_REG_G3, 0x5555)
# tracing all basic blocks with customized callback # tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block) mu.hook_add(UC_HOOK_BLOCK, hook_block)
@ -53,7 +53,7 @@ def test_sparc():
# now print out some registers # now print out some registers
print(">>> Emulation done. Below is the CPU context") print(">>> Emulation done. Below is the CPU context")
g3 = mu.reg_read(SPARC_REG_G3) g3 = mu.reg_read(UC_SPARC_REG_G3)
print(">>> G3 = 0x%x" %g3) print(">>> G3 = 0x%x" %g3)
except UcError as e: except UcError as e:

158
bindings/python/sample_x86.py
View file

@ -12,6 +12,7 @@ X86_CODE32_MEM_READ = b"\x8B\x0D\xAA\xAA\xAA\xAA\x41\x4a" # mov ecx,[0xaaaaaaaa]
X86_CODE32_MEM_WRITE = b"\x89\x0D\xAA\xAA\xAA\xAA\x41\x4a" # mov [0xaaaaaaaa], ecx; INC ecx; dec edx X86_CODE32_MEM_WRITE = b"\x89\x0D\xAA\xAA\xAA\xAA\x41\x4a" # mov [0xaaaaaaaa], ecx; INC ecx; dec edx
X86_CODE64 = b"\x41\xBC\x3B\xB0\x28\x2A\x49\x0F\xC9\x90\x4D\x0F\xAD\xCF\x49\x87\xFD\x90\x48\x81\xD2\x8A\xCE\x77\x35\x48\xF7\xD9\x4D\x29\xF4\x49\x81\xC9\xF6\x8A\xC6\x53\x4D\x87\xED\x48\x0F\xAD\xD2\x49\xF7\xD4\x48\xF7\xE1\x4D\x19\xC5\x4D\x89\xC5\x48\xF7\xD6\x41\xB8\x4F\x8D\x6B\x59\x4D\x87\xD0\x68\x6A\x1E\x09\x3C\x59" X86_CODE64 = b"\x41\xBC\x3B\xB0\x28\x2A\x49\x0F\xC9\x90\x4D\x0F\xAD\xCF\x49\x87\xFD\x90\x48\x81\xD2\x8A\xCE\x77\x35\x48\xF7\xD9\x4D\x29\xF4\x49\x81\xC9\xF6\x8A\xC6\x53\x4D\x87\xED\x48\x0F\xAD\xD2\x49\xF7\xD4\x48\xF7\xE1\x4D\x19\xC5\x4D\x89\xC5\x48\xF7\xD6\x41\xB8\x4F\x8D\x6B\x59\x4D\x87\xD0\x68\x6A\x1E\x09\x3C\x59"
X86_CODE32_INOUT = b"\x41\xE4\x3F\x4a\xE6\x46\x43" # INC ecx; IN AL, 0x3f; DEC edx; OUT 0x46, AL; INC ebx X86_CODE32_INOUT = b"\x41\xE4\x3F\x4a\xE6\x46\x43" # INC ecx; IN AL, 0x3f; DEC edx; OUT 0x46, AL; INC ebx
X86_CODE64_SYSCALL = '\x0f\x05' # SYSCALL
# memory address where emulation starts # memory address where emulation starts
ADDRESS = 0x1000000 ADDRESS = 0x1000000
@ -25,7 +26,7 @@ def hook_block(uc, address, size, user_data):
# callback for tracing instructions # callback for tracing instructions
def hook_code(uc, address, size, user_data): def hook_code(uc, address, size, user_data):
print(">>> Tracing instruction at 0x%x, instruction size = %u" %(address, size)) print(">>> Tracing instruction at 0x%x, instruction size = %u" %(address, size))
#eip = uc.reg_read(X86_REG_EIP) #eip = uc.reg_read(UC_X86_REG_EIP)
#print(">>> EIP = 0x%x" %(eip)) #print(">>> EIP = 0x%x" %(eip))
@ -55,7 +56,7 @@ def hook_mem_access(uc, access, address, size, value, user_data):
# callback for IN instruction # callback for IN instruction
def hook_in(uc, port, size, user_data): def hook_in(uc, port, size, user_data):
eip = uc.reg_read(X86_REG_EIP) eip = uc.reg_read(UC_X86_REG_EIP)
print("--- reading from port 0x%x, size: %u, address: 0x%x" %(port, size, eip)) print("--- reading from port 0x%x, size: %u, address: 0x%x" %(port, size, eip))
if size == 1: if size == 1:
# read 1 byte to AL # read 1 byte to AL
@ -72,20 +73,20 @@ def hook_in(uc, port, size, user_data):
# callback for OUT instruction # callback for OUT instruction
def hook_out(uc, port, size, value, user_data): def hook_out(uc, port, size, value, user_data):
eip = uc.reg_read(X86_REG_EIP) eip = uc.reg_read(UC_X86_REG_EIP)
print("--- writing to port 0x%x, size: %u, value: 0x%x, address: 0x%x" %(port, size, value, eip)) print("--- writing to port 0x%x, size: %u, value: 0x%x, address: 0x%x" %(port, size, value, eip))
# confirm that value is indeed the value of AL/AX/EAX # confirm that value is indeed the value of AL/AX/EAX
v = 0 v = 0
if size == 1: if size == 1:
# read 1 byte in AL # read 1 byte in AL
v = uc.reg_read(X86_REG_AL) v = uc.reg_read(UC_X86_REG_AL)
if size == 2: if size == 2:
# read 2 bytes in AX # read 2 bytes in AX
v = uc.reg_read(X86_REG_AX) v = uc.reg_read(UC_X86_REG_AX)
if size == 4: if size == 4:
# read 4 bytes in EAX # read 4 bytes in EAX
v = uc.reg_read(X86_REG_EAX) v = uc.reg_read(UC_X86_REG_EAX)
print("--- register value = 0x%x" %v) print("--- register value = 0x%x" %v)
@ -104,8 +105,8 @@ def test_i386():
mu.mem_write(ADDRESS, X86_CODE32) mu.mem_write(ADDRESS, X86_CODE32)
# initialize machine registers # initialize machine registers
mu.reg_write(X86_REG_ECX, 0x1234) mu.reg_write(UC_X86_REG_ECX, 0x1234)
mu.reg_write(X86_REG_EDX, 0x7890) mu.reg_write(UC_X86_REG_EDX, 0x7890)
# tracing all basic blocks with customized callback # tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block) mu.hook_add(UC_HOOK_BLOCK, hook_block)
@ -119,8 +120,8 @@ def test_i386():
# now print out some registers # now print out some registers
print(">>> Emulation done. Below is the CPU context") print(">>> Emulation done. Below is the CPU context")
r_ecx = mu.reg_read(X86_REG_ECX) r_ecx = mu.reg_read(UC_X86_REG_ECX)
r_edx = mu.reg_read(X86_REG_EDX) r_edx = mu.reg_read(UC_X86_REG_EDX)
print(">>> ECX = 0x%x" %r_ecx) print(">>> ECX = 0x%x" %r_ecx)
print(">>> EDX = 0x%x" %r_edx) print(">>> EDX = 0x%x" %r_edx)
@ -148,8 +149,8 @@ def test_i386_loop():
mu.mem_write(ADDRESS, X86_CODE32_LOOP) mu.mem_write(ADDRESS, X86_CODE32_LOOP)
# initialize machine registers # initialize machine registers
mu.reg_write(X86_REG_ECX, 0x1234) mu.reg_write(UC_X86_REG_ECX, 0x1234)
mu.reg_write(X86_REG_EDX, 0x7890) mu.reg_write(UC_X86_REG_EDX, 0x7890)
# emulate machine code in infinite time # emulate machine code in infinite time
mu.emu_start(ADDRESS, ADDRESS + len(X86_CODE32_LOOP), 2 * UC_SECOND_SCALE) mu.emu_start(ADDRESS, ADDRESS + len(X86_CODE32_LOOP), 2 * UC_SECOND_SCALE)
@ -157,8 +158,8 @@ def test_i386_loop():
# now print out some registers # now print out some registers
print(">>> Emulation done. Below is the CPU context") print(">>> Emulation done. Below is the CPU context")
r_ecx = mu.reg_read(X86_REG_ECX) r_ecx = mu.reg_read(UC_X86_REG_ECX)
r_edx = mu.reg_read(X86_REG_EDX) r_edx = mu.reg_read(UC_X86_REG_EDX)
print(">>> ECX = 0x%x" %r_ecx) print(">>> ECX = 0x%x" %r_ecx)
print(">>> EDX = 0x%x" %r_edx) print(">>> EDX = 0x%x" %r_edx)
@ -179,8 +180,8 @@ def test_i386_invalid_mem_read():
mu.mem_write(ADDRESS, X86_CODE32_MEM_READ) mu.mem_write(ADDRESS, X86_CODE32_MEM_READ)
# initialize machine registers # initialize machine registers
mu.reg_write(X86_REG_ECX, 0x1234) mu.reg_write(UC_X86_REG_ECX, 0x1234)
mu.reg_write(X86_REG_EDX, 0x7890) mu.reg_write(UC_X86_REG_EDX, 0x7890)
# tracing all basic blocks with customized callback # tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block) mu.hook_add(UC_HOOK_BLOCK, hook_block)
@ -197,8 +198,8 @@ def test_i386_invalid_mem_read():
# now print out some registers # now print out some registers
print(">>> Emulation done. Below is the CPU context") print(">>> Emulation done. Below is the CPU context")
r_ecx = mu.reg_read(X86_REG_ECX) r_ecx = mu.reg_read(UC_X86_REG_ECX)
r_edx = mu.reg_read(X86_REG_EDX) r_edx = mu.reg_read(UC_X86_REG_EDX)
print(">>> ECX = 0x%x" %r_ecx) print(">>> ECX = 0x%x" %r_ecx)
print(">>> EDX = 0x%x" %r_edx) print(">>> EDX = 0x%x" %r_edx)
@ -219,8 +220,8 @@ def test_i386_invalid_mem_write():
mu.mem_write(ADDRESS, X86_CODE32_MEM_WRITE) mu.mem_write(ADDRESS, X86_CODE32_MEM_WRITE)
# initialize machine registers # initialize machine registers
mu.reg_write(X86_REG_ECX, 0x1234) mu.reg_write(UC_X86_REG_ECX, 0x1234)
mu.reg_write(X86_REG_EDX, 0x7890) mu.reg_write(UC_X86_REG_EDX, 0x7890)
# tracing all basic blocks with customized callback # tracing all basic blocks with customized callback
#mu.hook_add(UC_HOOK_BLOCK, hook_block) #mu.hook_add(UC_HOOK_BLOCK, hook_block)
@ -240,8 +241,8 @@ def test_i386_invalid_mem_write():
# now print out some registers # now print out some registers
print(">>> Emulation done. Below is the CPU context") print(">>> Emulation done. Below is the CPU context")
r_ecx = mu.reg_read(X86_REG_ECX) r_ecx = mu.reg_read(UC_X86_REG_ECX)
r_edx = mu.reg_read(X86_REG_EDX) r_edx = mu.reg_read(UC_X86_REG_EDX)
print(">>> ECX = 0x%x" %r_ecx) print(">>> ECX = 0x%x" %r_ecx)
print(">>> EDX = 0x%x" %r_edx) print(">>> EDX = 0x%x" %r_edx)
@ -279,8 +280,8 @@ def test_i386_inout():
mu.mem_write(ADDRESS, X86_CODE32_INOUT) mu.mem_write(ADDRESS, X86_CODE32_INOUT)
# initialize machine registers # initialize machine registers
mu.reg_write(X86_REG_EAX, 0x1234) mu.reg_write(UC_X86_REG_EAX, 0x1234)
mu.reg_write(X86_REG_ECX, 0x6789) mu.reg_write(UC_X86_REG_ECX, 0x6789)
# tracing all basic blocks with customized callback # tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block) mu.hook_add(UC_HOOK_BLOCK, hook_block)
@ -289,8 +290,8 @@ def test_i386_inout():
mu.hook_add(UC_HOOK_CODE, hook_code) mu.hook_add(UC_HOOK_CODE, hook_code)
# handle IN & OUT instruction # handle IN & OUT instruction
mu.hook_add(UC_HOOK_INSN, hook_in, None, X86_INS_IN) mu.hook_add(UC_HOOK_INSN, hook_in, None, UC_X86_INS_IN)
mu.hook_add(UC_HOOK_INSN, hook_out, None, X86_INS_OUT) mu.hook_add(UC_HOOK_INSN, hook_out, None, UC_X86_INS_OUT)
# emulate machine code in infinite time # emulate machine code in infinite time
mu.emu_start(ADDRESS, ADDRESS + len(X86_CODE32_INOUT)) mu.emu_start(ADDRESS, ADDRESS + len(X86_CODE32_INOUT))
@ -298,8 +299,8 @@ def test_i386_inout():
# now print out some registers # now print out some registers
print(">>> Emulation done. Below is the CPU context") print(">>> Emulation done. Below is the CPU context")
r_ecx = mu.reg_read(X86_REG_ECX) r_ecx = mu.reg_read(UC_X86_REG_ECX)
r_eax = mu.reg_read(X86_REG_EAX) r_eax = mu.reg_read(UC_X86_REG_EAX)
print(">>> EAX = 0x%x" %r_eax) print(">>> EAX = 0x%x" %r_eax)
print(">>> ECX = 0x%x" %r_ecx) print(">>> ECX = 0x%x" %r_ecx)
except UcError as e: except UcError as e:
@ -319,23 +320,23 @@ def test_x86_64():
mu.mem_write(ADDRESS, X86_CODE64) mu.mem_write(ADDRESS, X86_CODE64)
# initialize machine registers # initialize machine registers
mu.reg_write(X86_REG_RAX, 0x71f3029efd49d41d) mu.reg_write(UC_X86_REG_RAX, 0x71f3029efd49d41d)
mu.reg_write(X86_REG_RBX, 0xd87b45277f133ddb) mu.reg_write(UC_X86_REG_RBX, 0xd87b45277f133ddb)
mu.reg_write(X86_REG_RCX, 0xab40d1ffd8afc461) mu.reg_write(UC_X86_REG_RCX, 0xab40d1ffd8afc461)
mu.reg_write(X86_REG_RDX, 0x919317b4a733f01) mu.reg_write(UC_X86_REG_RDX, 0x919317b4a733f01)
mu.reg_write(X86_REG_RSI, 0x4c24e753a17ea358) mu.reg_write(UC_X86_REG_RSI, 0x4c24e753a17ea358)
mu.reg_write(X86_REG_RDI, 0xe509a57d2571ce96) mu.reg_write(UC_X86_REG_RDI, 0xe509a57d2571ce96)
mu.reg_write(X86_REG_R8, 0xea5b108cc2b9ab1f) mu.reg_write(UC_X86_REG_R8, 0xea5b108cc2b9ab1f)
mu.reg_write(X86_REG_R9, 0x19ec097c8eb618c1) mu.reg_write(UC_X86_REG_R9, 0x19ec097c8eb618c1)
mu.reg_write(X86_REG_R10, 0xec45774f00c5f682) mu.reg_write(UC_X86_REG_R10, 0xec45774f00c5f682)
mu.reg_write(X86_REG_R11, 0xe17e9dbec8c074aa) mu.reg_write(UC_X86_REG_R11, 0xe17e9dbec8c074aa)
mu.reg_write(X86_REG_R12, 0x80f86a8dc0f6d457) mu.reg_write(UC_X86_REG_R12, 0x80f86a8dc0f6d457)
mu.reg_write(X86_REG_R13, 0x48288ca5671c5492) mu.reg_write(UC_X86_REG_R13, 0x48288ca5671c5492)
mu.reg_write(X86_REG_R14, 0x595f72f6e4017f6e) mu.reg_write(UC_X86_REG_R14, 0x595f72f6e4017f6e)
mu.reg_write(X86_REG_R15, 0x1efd97aea331cccc) mu.reg_write(UC_X86_REG_R15, 0x1efd97aea331cccc)
# setup stack # setup stack
mu.reg_write(X86_REG_RSP, ADDRESS + 0x200000) mu.reg_write(UC_X86_REG_RSP, ADDRESS + 0x200000)
# tracing all basic blocks with customized callback # tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block) mu.hook_add(UC_HOOK_BLOCK, hook_block)
@ -358,20 +359,20 @@ def test_x86_64():
# now print out some registers # now print out some registers
print(">>> Emulation done. Below is the CPU context") print(">>> Emulation done. Below is the CPU context")
rax = mu.reg_read(X86_REG_RAX) rax = mu.reg_read(UC_X86_REG_RAX)
rbx = mu.reg_read(X86_REG_RBX) rbx = mu.reg_read(UC_X86_REG_RBX)
rcx = mu.reg_read(X86_REG_RCX) rcx = mu.reg_read(UC_X86_REG_RCX)
rdx = mu.reg_read(X86_REG_RDX) rdx = mu.reg_read(UC_X86_REG_RDX)
rsi = mu.reg_read(X86_REG_RSI) rsi = mu.reg_read(UC_X86_REG_RSI)
rdi = mu.reg_read(X86_REG_RDI) rdi = mu.reg_read(UC_X86_REG_RDI)
r8 = mu.reg_read(X86_REG_R8) r8 = mu.reg_read(UC_X86_REG_R8)
r9 = mu.reg_read(X86_REG_R9) r9 = mu.reg_read(UC_X86_REG_R9)
r10 = mu.reg_read(X86_REG_R10) r10 = mu.reg_read(UC_X86_REG_R10)
r11 = mu.reg_read(X86_REG_R11) r11 = mu.reg_read(UC_X86_REG_R11)
r12 = mu.reg_read(X86_REG_R12) r12 = mu.reg_read(UC_X86_REG_R12)
r13 = mu.reg_read(X86_REG_R13) r13 = mu.reg_read(UC_X86_REG_R13)
r14 = mu.reg_read(X86_REG_R14) r14 = mu.reg_read(UC_X86_REG_R14)
r15 = mu.reg_read(X86_REG_R15) r15 = mu.reg_read(UC_X86_REG_R15)
print(">>> RAX = %x" %rax) print(">>> RAX = %x" %rax)
print(">>> RBX = %x" %rbx) print(">>> RBX = %x" %rbx)
@ -395,6 +396,47 @@ def test_x86_64():
print("ERROR: %s" % e) print("ERROR: %s" % e)
def test_x86_64_syscall():
print("Emulate x86_64 code with 'syscall' instruction")
try:
# Initialize emulator in X86-64bit mode
mu = Uc(UC_ARCH_X86, UC_MODE_64)
# map 2MB memory for this emulation
mu.mem_map(ADDRESS, 2 * 1024 * 1024)
# write machine code to be emulated to memory
mu.mem_write(ADDRESS, X86_CODE64_SYSCALL)
def hook_syscall(mu, user_data):
rax = mu.reg_read(UC_X86_REG_RAX)
if rax == 0x100:
mu.reg_write(UC_X86_REG_RAX, 0x200)
else:
print('ERROR: was not expecting rax=%d in syscall' % rax)
# hook interrupts for syscall
mu.hook_add(UC_HOOK_INSN, hook_syscall, None, UC_X86_INS_SYSCALL)
# syscall handler is expecting rax=0x100
mu.reg_write(UC_X86_REG_RAX, 0x100)
try:
# emulate machine code in infinite time
mu.emu_start(ADDRESS, ADDRESS + len(X86_CODE64_SYSCALL))
except UcError as e:
print("ERROR: %s" % e)
# now print out some registers
print(">>> Emulation done. Below is the CPU context")
rax = mu.reg_read(UC_X86_REG_RAX)
print(">>> RAX = 0x%x" % rax)
except UcError as e:
print("ERROR: %s" % e)
if __name__ == '__main__': if __name__ == '__main__':
test_i386() test_i386()
print("=" * 20) print("=" * 20)
@ -407,3 +449,5 @@ if __name__ == '__main__':
test_i386_inout() test_i386_inout()
print("=" * 20) print("=" * 20)
test_x86_64() test_x86_64()
print("=" * 20)
test_x86_64_syscall()

27
bindings/python/shellcode.py
View file

@ -40,16 +40,16 @@ def hook_intr(uc, intno, user_data):
uc.emu_stop() uc.emu_stop()
return return
eax = uc.reg_read(X86_REG_EAX) eax = uc.reg_read(UC_X86_REG_EAX)
eip = uc.reg_read(X86_REG_EIP) eip = uc.reg_read(UC_X86_REG_EIP)
if eax == 1: # sys_exit if eax == 1: # sys_exit
print(">>> 0x%x: interrupt 0x%x, EAX = 0x%x" %(eip, intno, eax)) print(">>> 0x%x: interrupt 0x%x, EAX = 0x%x" %(eip, intno, eax))
uc.emu_stop() uc.emu_stop()
elif eax == 4: # sys_write elif eax == 4: # sys_write
# ECX = buffer address # ECX = buffer address
ecx = uc.reg_read(X86_REG_ECX) ecx = uc.reg_read(UC_X86_REG_ECX)
# EDX = buffer size # EDX = buffer size
edx = uc.reg_read(X86_REG_EDX) edx = uc.reg_read(UC_X86_REG_EDX)
try: try:
buf = uc.mem_read(ecx, edx) buf = uc.mem_read(ecx, edx)
@ -65,6 +65,12 @@ def hook_intr(uc, intno, user_data):
print(">>> 0x%x: interrupt 0x%x, EAX = 0x%x" %(eip, intno, eax)) print(">>> 0x%x: interrupt 0x%x, EAX = 0x%x" %(eip, intno, eax))
def hook_syscall(mu, user_data):
rax = mu.reg_read(UC_X86_REG_RAX)
print(">>> got SYSCALL with RAX = 0x%x" %(rax))
mu.emu_stop()
# Test X86 32 bit # Test X86 32 bit
def test_i386(mode, code): def test_i386(mode, code):
print("Emulate x86 code") print("Emulate x86 code")
@ -79,7 +85,7 @@ def test_i386(mode, code):
mu.mem_write(ADDRESS, code) mu.mem_write(ADDRESS, code)
# initialize stack # initialize stack
mu.reg_write(X86_REG_ESP, ADDRESS + 0x200000) mu.reg_write(UC_X86_REG_ESP, ADDRESS + 0x200000)
# tracing all basic blocks with customized callback # tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block) mu.hook_add(UC_HOOK_BLOCK, hook_block)
@ -90,6 +96,9 @@ def test_i386(mode, code):
# handle interrupt ourself # handle interrupt ourself
mu.hook_add(UC_HOOK_INTR, hook_intr) mu.hook_add(UC_HOOK_INTR, hook_intr)
# handle SYSCALL
mu.hook_add(UC_HOOK_INSN, hook_syscall, None, UC_X86_INS_SYSCALL)
# emulate machine code in infinite time # emulate machine code in infinite time
mu.emu_start(ADDRESS, ADDRESS + len(code)) mu.emu_start(ADDRESS, ADDRESS + len(code))
@ -102,9 +111,9 @@ def test_i386(mode, code):
if __name__ == '__main__': if __name__ == '__main__':
#test_i386(UC_MODE_32, X86_CODE32_SELF) test_i386(UC_MODE_32, X86_CODE32_SELF)
#print("=" * 20) print("=" * 20)
#test_i386(UC_MODE_32, X86_CODE32) test_i386(UC_MODE_32, X86_CODE32)
#print("=" * 20) print("=" * 20)
test_i386(UC_MODE_64, X86_CODE64) # FIXME test_i386(UC_MODE_64, X86_CODE64) # FIXME

32
bindings/python/unicorn/__init__.py
View file

@ -9,7 +9,7 @@ __all__ = [
'Uc', 'Uc',
'uc_version', 'uc_version',
'uc_support', 'uc_arch_supported',
'version_bind', 'version_bind',
'debug', 'debug',
@ -53,6 +53,7 @@ __all__ = [
'UC_ERR_CODE_INVALID', 'UC_ERR_CODE_INVALID',
'UC_ERR_HOOK', 'UC_ERR_HOOK',
'UC_ERR_INSN_INVALID', 'UC_ERR_INSN_INVALID',
'UC_ERR_MAP',
'UC_HOOK_INTR', 'UC_HOOK_INTR',
'UC_HOOK_INSN', 'UC_HOOK_INSN',
@ -122,6 +123,7 @@ UC_ERR_MEM_WRITE = 8 # Quit emulation due to invalid memory WRITE: uc_emu_st
UC_ERR_CODE_INVALID = 9 # Quit emulation due to invalid code address: uc_emu_start() UC_ERR_CODE_INVALID = 9 # Quit emulation due to invalid code address: uc_emu_start()
UC_ERR_HOOK = 10 # Invalid hook type: uc_hook_add() UC_ERR_HOOK = 10 # Invalid hook type: uc_hook_add()
UC_ERR_INSN_INVALID = 11 # Invalid instruction UC_ERR_INSN_INVALID = 11 # Invalid instruction
UC_ERR_MAP = 12 # Invalid memory mapping
# All type of hooks for uc_hook_add() API. # All type of hooks for uc_hook_add() API.
@ -202,7 +204,7 @@ def _setup_prototype(lib, fname, restype, *argtypes):
getattr(lib, fname).argtypes = argtypes getattr(lib, fname).argtypes = argtypes
_setup_prototype(_uc, "uc_version", ctypes.c_int, ctypes.POINTER(ctypes.c_int), ctypes.POINTER(ctypes.c_int)) _setup_prototype(_uc, "uc_version", ctypes.c_int, ctypes.POINTER(ctypes.c_int), ctypes.POINTER(ctypes.c_int))
_setup_prototype(_uc, "uc_support", ctypes.c_bool, ctypes.c_int) _setup_prototype(_uc, "uc_arch_supported", ctypes.c_bool, ctypes.c_int)
_setup_prototype(_uc, "uc_open", ctypes.c_int, ctypes.c_uint, ctypes.c_uint, ctypes.POINTER(ctypes.c_size_t)) _setup_prototype(_uc, "uc_open", ctypes.c_int, ctypes.c_uint, ctypes.c_uint, ctypes.POINTER(ctypes.c_size_t))
_setup_prototype(_uc, "uc_close", ctypes.c_int, ctypes.POINTER(ctypes.c_size_t)) _setup_prototype(_uc, "uc_close", ctypes.c_int, ctypes.POINTER(ctypes.c_size_t))
_setup_prototype(_uc, "uc_strerror", ctypes.c_char_p, ctypes.c_int) _setup_prototype(_uc, "uc_strerror", ctypes.c_char_p, ctypes.c_int)
@ -231,6 +233,7 @@ UC_HOOK_INSN_IN_CB = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.c_size_t, ctypes.c
ctypes.c_int, ctypes.c_void_p) ctypes.c_int, ctypes.c_void_p)
UC_HOOK_INSN_OUT_CB = ctypes.CFUNCTYPE(None, ctypes.c_size_t, ctypes.c_uint32, \ UC_HOOK_INSN_OUT_CB = ctypes.CFUNCTYPE(None, ctypes.c_size_t, ctypes.c_uint32, \
ctypes.c_int, ctypes.c_uint32, ctypes.c_void_p) ctypes.c_int, ctypes.c_uint32, ctypes.c_void_p)
UC_HOOK_INSN_SYSCALL_CB = ctypes.CFUNCTYPE(None, ctypes.c_size_t, ctypes.c_void_p)
# access to error code via @errno of UcError # access to error code via @errno of UcError
@ -256,8 +259,8 @@ def version_bind():
# check to see if this engine supports a particular arch # check to see if this engine supports a particular arch
def uc_support(query): def uc_arch_supported(query):
return _uc.uc_support(query) return _uc.uc_arch_supported(query)
class Uc(object): class Uc(object):
@ -383,6 +386,12 @@ class Uc(object):
cb(self, port, size, value, data) cb(self, port, size, value, data)
def _hook_insn_syscall_cb(self, handle, user_data):
# call user's callback with self object
(cb, data) = self._callbacks[user_data]
cb(self, data)
# add a hook # add a hook
def hook_add(self, htype, callback, user_data=None, arg1=1, arg2=0): def hook_add(self, htype, callback, user_data=None, arg1=1, arg2=0):
_h2 = ctypes.c_size_t() _h2 = ctypes.c_size_t()
@ -409,10 +418,12 @@ class Uc(object):
cb, ctypes.cast(self._callback_count, ctypes.c_void_p)) cb, ctypes.cast(self._callback_count, ctypes.c_void_p))
elif htype == UC_HOOK_INSN: elif htype == UC_HOOK_INSN:
insn = ctypes.c_int(arg1) insn = ctypes.c_int(arg1)
if arg1 == x86_const.X86_INS_IN: # IN instruction if arg1 == x86_const.UC_X86_INS_IN: # IN instruction
cb = ctypes.cast(UC_HOOK_INSN_IN_CB(self._hook_insn_in_cb), UC_HOOK_INSN_IN_CB) cb = ctypes.cast(UC_HOOK_INSN_IN_CB(self._hook_insn_in_cb), UC_HOOK_INSN_IN_CB)
if arg1 == x86_const.X86_INS_OUT: # OUT instruction if arg1 == x86_const.UC_X86_INS_OUT: # OUT instruction
cb = ctypes.cast(UC_HOOK_INSN_OUT_CB(self._hook_insn_out_cb), UC_HOOK_INSN_OUT_CB) cb = ctypes.cast(UC_HOOK_INSN_OUT_CB(self._hook_insn_out_cb), UC_HOOK_INSN_OUT_CB)
if arg1 in (x86_const.UC_X86_INS_SYSCALL, x86_const.UC_X86_INS_SYSENTER): # SYSCALL/SYSENTER instruction
cb = ctypes.cast(UC_HOOK_INSN_SYSCALL_CB(self._hook_insn_syscall_cb), UC_HOOK_INSN_SYSCALL_CB)
status = _uc.uc_hook_add(self._uch, ctypes.byref(_h2), htype, \ status = _uc.uc_hook_add(self._uch, ctypes.byref(_h2), htype, \
cb, ctypes.cast(self._callback_count, ctypes.c_void_p), insn) cb, ctypes.cast(self._callback_count, ctypes.c_void_p), insn)
elif htype == UC_HOOK_INTR: elif htype == UC_HOOK_INTR:
@ -439,20 +450,15 @@ class Uc(object):
def debug(): def debug():
archs = { "arm": UC_ARCH_ARM, "arm64": UC_ARCH_ARM64, \ archs = { "arm": UC_ARCH_ARM, "arm64": UC_ARCH_ARM64, \
"mips": UC_ARCH_MIPS, "sparc": UC_ARCH_SPARC, \ "mips": UC_ARCH_MIPS, "sparc": UC_ARCH_SPARC, \
"m68k": UC_ARCH_M68K } "m68k": UC_ARCH_M68K, "x86": UC_ARCH_X86 }
all_archs = "" all_archs = ""
keys = archs.keys() keys = archs.keys()
keys.sort() keys.sort()
for k in keys: for k in keys:
if uc_support(archs[k]): if uc_arch_supported(archs[k]):
all_archs += "-%s" % k all_archs += "-%s" % k
if uc_support(UC_ARCH_X86):
all_archs += "-x86"
if uc_support(UC_SUPPORT_X86_REDUCE):
all_archs += "_reduce"
(major, minor, _combined) = uc_version() (major, minor, _combined) = uc_version()
return "python-%s-c%u.%u-b%u.%u" % (all_archs, major, minor, UC_API_MAJOR, UC_API_MINOR) return "python-%s-c%u.%u-b%u.%u" % (all_archs, major, minor, UC_API_MAJOR, UC_API_MINOR)

532
bindings/python/unicorn/arm64_const.py
View file

@ -2,273 +2,273 @@
# ARM64 registers # ARM64 registers
ARM64_REG_INVALID = 0 UC_ARM64_REG_INVALID = 0
ARM64_REG_X29 = 1 UC_ARM64_REG_X29 = 1
ARM64_REG_X30 = 2 UC_ARM64_REG_X30 = 2
ARM64_REG_NZCV = 3 UC_ARM64_REG_NZCV = 3
ARM64_REG_SP = 4 UC_ARM64_REG_SP = 4
ARM64_REG_WSP = 5 UC_ARM64_REG_WSP = 5
ARM64_REG_WZR = 6 UC_ARM64_REG_WZR = 6
ARM64_REG_XZR = 7 UC_ARM64_REG_XZR = 7
ARM64_REG_B0 = 8 UC_ARM64_REG_B0 = 8
ARM64_REG_B1 = 9 UC_ARM64_REG_B1 = 9
ARM64_REG_B2 = 10 UC_ARM64_REG_B2 = 10
ARM64_REG_B3 = 11 UC_ARM64_REG_B3 = 11
ARM64_REG_B4 = 12 UC_ARM64_REG_B4 = 12
ARM64_REG_B5 = 13 UC_ARM64_REG_B5 = 13
ARM64_REG_B6 = 14 UC_ARM64_REG_B6 = 14
ARM64_REG_B7 = 15 UC_ARM64_REG_B7 = 15
ARM64_REG_B8 = 16 UC_ARM64_REG_B8 = 16
ARM64_REG_B9 = 17 UC_ARM64_REG_B9 = 17
ARM64_REG_B10 = 18 UC_ARM64_REG_B10 = 18
ARM64_REG_B11 = 19 UC_ARM64_REG_B11 = 19
ARM64_REG_B12 = 20 UC_ARM64_REG_B12 = 20
ARM64_REG_B13 = 21 UC_ARM64_REG_B13 = 21
ARM64_REG_B14 = 22 UC_ARM64_REG_B14 = 22
ARM64_REG_B15 = 23 UC_ARM64_REG_B15 = 23
ARM64_REG_B16 = 24 UC_ARM64_REG_B16 = 24
ARM64_REG_B17 = 25 UC_ARM64_REG_B17 = 25
ARM64_REG_B18 = 26 UC_ARM64_REG_B18 = 26
ARM64_REG_B19 = 27 UC_ARM64_REG_B19 = 27
ARM64_REG_B20 = 28 UC_ARM64_REG_B20 = 28
ARM64_REG_B21 = 29 UC_ARM64_REG_B21 = 29
ARM64_REG_B22 = 30 UC_ARM64_REG_B22 = 30
ARM64_REG_B23 = 31 UC_ARM64_REG_B23 = 31
ARM64_REG_B24 = 32 UC_ARM64_REG_B24 = 32
ARM64_REG_B25 = 33 UC_ARM64_REG_B25 = 33
ARM64_REG_B26 = 34 UC_ARM64_REG_B26 = 34
ARM64_REG_B27 = 35 UC_ARM64_REG_B27 = 35
ARM64_REG_B28 = 36 UC_ARM64_REG_B28 = 36
ARM64_REG_B29 = 37 UC_ARM64_REG_B29 = 37
ARM64_REG_B30 = 38 UC_ARM64_REG_B30 = 38
ARM64_REG_B31 = 39 UC_ARM64_REG_B31 = 39
ARM64_REG_D0 = 40 UC_ARM64_REG_D0 = 40
ARM64_REG_D1 = 41 UC_ARM64_REG_D1 = 41
ARM64_REG_D2 = 42 UC_ARM64_REG_D2 = 42
ARM64_REG_D3 = 43 UC_ARM64_REG_D3 = 43
ARM64_REG_D4 = 44 UC_ARM64_REG_D4 = 44
ARM64_REG_D5 = 45 UC_ARM64_REG_D5 = 45
ARM64_REG_D6 = 46 UC_ARM64_REG_D6 = 46
ARM64_REG_D7 = 47 UC_ARM64_REG_D7 = 47
ARM64_REG_D8 = 48 UC_ARM64_REG_D8 = 48
ARM64_REG_D9 = 49 UC_ARM64_REG_D9 = 49
ARM64_REG_D10 = 50 UC_ARM64_REG_D10 = 50
ARM64_REG_D11 = 51 UC_ARM64_REG_D11 = 51
ARM64_REG_D12 = 52 UC_ARM64_REG_D12 = 52
ARM64_REG_D13 = 53 UC_ARM64_REG_D13 = 53
ARM64_REG_D14 = 54 UC_ARM64_REG_D14 = 54
ARM64_REG_D15 = 55 UC_ARM64_REG_D15 = 55
ARM64_REG_D16 = 56 UC_ARM64_REG_D16 = 56
ARM64_REG_D17 = 57 UC_ARM64_REG_D17 = 57
ARM64_REG_D18 = 58 UC_ARM64_REG_D18 = 58
ARM64_REG_D19 = 59 UC_ARM64_REG_D19 = 59
ARM64_REG_D20 = 60 UC_ARM64_REG_D20 = 60
ARM64_REG_D21 = 61 UC_ARM64_REG_D21 = 61
ARM64_REG_D22 = 62 UC_ARM64_REG_D22 = 62
ARM64_REG_D23 = 63 UC_ARM64_REG_D23 = 63
ARM64_REG_D24 = 64 UC_ARM64_REG_D24 = 64
ARM64_REG_D25 = 65 UC_ARM64_REG_D25 = 65
ARM64_REG_D26 = 66 UC_ARM64_REG_D26 = 66
ARM64_REG_D27 = 67 UC_ARM64_REG_D27 = 67
ARM64_REG_D28 = 68 UC_ARM64_REG_D28 = 68
ARM64_REG_D29 = 69 UC_ARM64_REG_D29 = 69
ARM64_REG_D30 = 70 UC_ARM64_REG_D30 = 70
ARM64_REG_D31 = 71 UC_ARM64_REG_D31 = 71
ARM64_REG_H0 = 72 UC_ARM64_REG_H0 = 72
ARM64_REG_H1 = 73 UC_ARM64_REG_H1 = 73
ARM64_REG_H2 = 74 UC_ARM64_REG_H2 = 74
ARM64_REG_H3 = 75 UC_ARM64_REG_H3 = 75
ARM64_REG_H4 = 76 UC_ARM64_REG_H4 = 76
ARM64_REG_H5 = 77 UC_ARM64_REG_H5 = 77
ARM64_REG_H6 = 78 UC_ARM64_REG_H6 = 78
ARM64_REG_H7 = 79 UC_ARM64_REG_H7 = 79
ARM64_REG_H8 = 80 UC_ARM64_REG_H8 = 80
ARM64_REG_H9 = 81 UC_ARM64_REG_H9 = 81
ARM64_REG_H10 = 82 UC_ARM64_REG_H10 = 82
ARM64_REG_H11 = 83 UC_ARM64_REG_H11 = 83
ARM64_REG_H12 = 84 UC_ARM64_REG_H12 = 84
ARM64_REG_H13 = 85 UC_ARM64_REG_H13 = 85
ARM64_REG_H14 = 86 UC_ARM64_REG_H14 = 86
ARM64_REG_H15 = 87 UC_ARM64_REG_H15 = 87
ARM64_REG_H16 = 88 UC_ARM64_REG_H16 = 88
ARM64_REG_H17 = 89 UC_ARM64_REG_H17 = 89
ARM64_REG_H18 = 90 UC_ARM64_REG_H18 = 90
ARM64_REG_H19 = 91 UC_ARM64_REG_H19 = 91
ARM64_REG_H20 = 92 UC_ARM64_REG_H20 = 92
ARM64_REG_H21 = 93 UC_ARM64_REG_H21 = 93
ARM64_REG_H22 = 94 UC_ARM64_REG_H22 = 94
ARM64_REG_H23 = 95 UC_ARM64_REG_H23 = 95
ARM64_REG_H24 = 96 UC_ARM64_REG_H24 = 96
ARM64_REG_H25 = 97 UC_ARM64_REG_H25 = 97
ARM64_REG_H26 = 98 UC_ARM64_REG_H26 = 98
ARM64_REG_H27 = 99 UC_ARM64_REG_H27 = 99
ARM64_REG_H28 = 100 UC_ARM64_REG_H28 = 100
ARM64_REG_H29 = 101 UC_ARM64_REG_H29 = 101
ARM64_REG_H30 = 102 UC_ARM64_REG_H30 = 102
ARM64_REG_H31 = 103 UC_ARM64_REG_H31 = 103
ARM64_REG_Q0 = 104 UC_ARM64_REG_Q0 = 104
ARM64_REG_Q1 = 105 UC_ARM64_REG_Q1 = 105
ARM64_REG_Q2 = 106 UC_ARM64_REG_Q2 = 106
ARM64_REG_Q3 = 107 UC_ARM64_REG_Q3 = 107
ARM64_REG_Q4 = 108 UC_ARM64_REG_Q4 = 108
ARM64_REG_Q5 = 109 UC_ARM64_REG_Q5 = 109
ARM64_REG_Q6 = 110 UC_ARM64_REG_Q6 = 110
ARM64_REG_Q7 = 111 UC_ARM64_REG_Q7 = 111
ARM64_REG_Q8 = 112 UC_ARM64_REG_Q8 = 112
ARM64_REG_Q9 = 113 UC_ARM64_REG_Q9 = 113
ARM64_REG_Q10 = 114 UC_ARM64_REG_Q10 = 114
ARM64_REG_Q11 = 115 UC_ARM64_REG_Q11 = 115
ARM64_REG_Q12 = 116 UC_ARM64_REG_Q12 = 116
ARM64_REG_Q13 = 117 UC_ARM64_REG_Q13 = 117
ARM64_REG_Q14 = 118 UC_ARM64_REG_Q14 = 118
ARM64_REG_Q15 = 119 UC_ARM64_REG_Q15 = 119
ARM64_REG_Q16 = 120 UC_ARM64_REG_Q16 = 120
ARM64_REG_Q17 = 121 UC_ARM64_REG_Q17 = 121
ARM64_REG_Q18 = 122 UC_ARM64_REG_Q18 = 122
ARM64_REG_Q19 = 123 UC_ARM64_REG_Q19 = 123
ARM64_REG_Q20 = 124 UC_ARM64_REG_Q20 = 124
ARM64_REG_Q21 = 125 UC_ARM64_REG_Q21 = 125
ARM64_REG_Q22 = 126 UC_ARM64_REG_Q22 = 126
ARM64_REG_Q23 = 127 UC_ARM64_REG_Q23 = 127
ARM64_REG_Q24 = 128 UC_ARM64_REG_Q24 = 128
ARM64_REG_Q25 = 129 UC_ARM64_REG_Q25 = 129
ARM64_REG_Q26 = 130 UC_ARM64_REG_Q26 = 130
ARM64_REG_Q27 = 131 UC_ARM64_REG_Q27 = 131
ARM64_REG_Q28 = 132 UC_ARM64_REG_Q28 = 132
ARM64_REG_Q29 = 133 UC_ARM64_REG_Q29 = 133
ARM64_REG_Q30 = 134 UC_ARM64_REG_Q30 = 134
ARM64_REG_Q31 = 135 UC_ARM64_REG_Q31 = 135
ARM64_REG_S0 = 136 UC_ARM64_REG_S0 = 136
ARM64_REG_S1 = 137 UC_ARM64_REG_S1 = 137
ARM64_REG_S2 = 138 UC_ARM64_REG_S2 = 138
ARM64_REG_S3 = 139 UC_ARM64_REG_S3 = 139
ARM64_REG_S4 = 140 UC_ARM64_REG_S4 = 140
ARM64_REG_S5 = 141 UC_ARM64_REG_S5 = 141
ARM64_REG_S6 = 142 UC_ARM64_REG_S6 = 142
ARM64_REG_S7 = 143 UC_ARM64_REG_S7 = 143
ARM64_REG_S8 = 144 UC_ARM64_REG_S8 = 144
ARM64_REG_S9 = 145 UC_ARM64_REG_S9 = 145
ARM64_REG_S10 = 146 UC_ARM64_REG_S10 = 146
ARM64_REG_S11 = 147 UC_ARM64_REG_S11 = 147
ARM64_REG_S12 = 148 UC_ARM64_REG_S12 = 148
ARM64_REG_S13 = 149 UC_ARM64_REG_S13 = 149
ARM64_REG_S14 = 150 UC_ARM64_REG_S14 = 150
ARM64_REG_S15 = 151 UC_ARM64_REG_S15 = 151
ARM64_REG_S16 = 152 UC_ARM64_REG_S16 = 152
ARM64_REG_S17 = 153 UC_ARM64_REG_S17 = 153
ARM64_REG_S18 = 154 UC_ARM64_REG_S18 = 154
ARM64_REG_S19 = 155 UC_ARM64_REG_S19 = 155
ARM64_REG_S20 = 156 UC_ARM64_REG_S20 = 156
ARM64_REG_S21 = 157 UC_ARM64_REG_S21 = 157
ARM64_REG_S22 = 158 UC_ARM64_REG_S22 = 158
ARM64_REG_S23 = 159 UC_ARM64_REG_S23 = 159
ARM64_REG_S24 = 160 UC_ARM64_REG_S24 = 160
ARM64_REG_S25 = 161 UC_ARM64_REG_S25 = 161
ARM64_REG_S26 = 162 UC_ARM64_REG_S26 = 162
ARM64_REG_S27 = 163 UC_ARM64_REG_S27 = 163
ARM64_REG_S28 = 164 UC_ARM64_REG_S28 = 164
ARM64_REG_S29 = 165 UC_ARM64_REG_S29 = 165
ARM64_REG_S30 = 166 UC_ARM64_REG_S30 = 166
ARM64_REG_S31 = 167 UC_ARM64_REG_S31 = 167
ARM64_REG_W0 = 168 UC_ARM64_REG_W0 = 168
ARM64_REG_W1 = 169 UC_ARM64_REG_W1 = 169
ARM64_REG_W2 = 170 UC_ARM64_REG_W2 = 170
ARM64_REG_W3 = 171 UC_ARM64_REG_W3 = 171
ARM64_REG_W4 = 172 UC_ARM64_REG_W4 = 172
ARM64_REG_W5 = 173 UC_ARM64_REG_W5 = 173
ARM64_REG_W6 = 174 UC_ARM64_REG_W6 = 174
ARM64_REG_W7 = 175 UC_ARM64_REG_W7 = 175
ARM64_REG_W8 = 176 UC_ARM64_REG_W8 = 176
ARM64_REG_W9 = 177 UC_ARM64_REG_W9 = 177
ARM64_REG_W10 = 178 UC_ARM64_REG_W10 = 178
ARM64_REG_W11 = 179 UC_ARM64_REG_W11 = 179
ARM64_REG_W12 = 180 UC_ARM64_REG_W12 = 180
ARM64_REG_W13 = 181 UC_ARM64_REG_W13 = 181
ARM64_REG_W14 = 182 UC_ARM64_REG_W14 = 182
ARM64_REG_W15 = 183 UC_ARM64_REG_W15 = 183
ARM64_REG_W16 = 184 UC_ARM64_REG_W16 = 184
ARM64_REG_W17 = 185 UC_ARM64_REG_W17 = 185
ARM64_REG_W18 = 186 UC_ARM64_REG_W18 = 186
ARM64_REG_W19 = 187 UC_ARM64_REG_W19 = 187
ARM64_REG_W20 = 188 UC_ARM64_REG_W20 = 188
ARM64_REG_W21 = 189 UC_ARM64_REG_W21 = 189
ARM64_REG_W22 = 190 UC_ARM64_REG_W22 = 190
ARM64_REG_W23 = 191 UC_ARM64_REG_W23 = 191
ARM64_REG_W24 = 192 UC_ARM64_REG_W24 = 192
ARM64_REG_W25 = 193 UC_ARM64_REG_W25 = 193
ARM64_REG_W26 = 194 UC_ARM64_REG_W26 = 194
ARM64_REG_W27 = 195 UC_ARM64_REG_W27 = 195
ARM64_REG_W28 = 196 UC_ARM64_REG_W28 = 196
ARM64_REG_W29 = 197 UC_ARM64_REG_W29 = 197
ARM64_REG_W30 = 198 UC_ARM64_REG_W30 = 198
ARM64_REG_X0 = 199 UC_ARM64_REG_X0 = 199
ARM64_REG_X1 = 200 UC_ARM64_REG_X1 = 200
ARM64_REG_X2 = 201 UC_ARM64_REG_X2 = 201
ARM64_REG_X3 = 202 UC_ARM64_REG_X3 = 202
ARM64_REG_X4 = 203 UC_ARM64_REG_X4 = 203
ARM64_REG_X5 = 204 UC_ARM64_REG_X5 = 204
ARM64_REG_X6 = 205 UC_ARM64_REG_X6 = 205
ARM64_REG_X7 = 206 UC_ARM64_REG_X7 = 206
ARM64_REG_X8 = 207 UC_ARM64_REG_X8 = 207
ARM64_REG_X9 = 208 UC_ARM64_REG_X9 = 208
ARM64_REG_X10 = 209 UC_ARM64_REG_X10 = 209
ARM64_REG_X11 = 210 UC_ARM64_REG_X11 = 210
ARM64_REG_X12 = 211 UC_ARM64_REG_X12 = 211
ARM64_REG_X13 = 212 UC_ARM64_REG_X13 = 212
ARM64_REG_X14 = 213 UC_ARM64_REG_X14 = 213
ARM64_REG_X15 = 214 UC_ARM64_REG_X15 = 214
ARM64_REG_X16 = 215 UC_ARM64_REG_X16 = 215
ARM64_REG_X17 = 216 UC_ARM64_REG_X17 = 216
ARM64_REG_X18 = 217 UC_ARM64_REG_X18 = 217
ARM64_REG_X19 = 218 UC_ARM64_REG_X19 = 218
ARM64_REG_X20 = 219 UC_ARM64_REG_X20 = 219
ARM64_REG_X21 = 220 UC_ARM64_REG_X21 = 220
ARM64_REG_X22 = 221 UC_ARM64_REG_X22 = 221
ARM64_REG_X23 = 222 UC_ARM64_REG_X23 = 222
ARM64_REG_X24 = 223 UC_ARM64_REG_X24 = 223
ARM64_REG_X25 = 224 UC_ARM64_REG_X25 = 224
ARM64_REG_X26 = 225 UC_ARM64_REG_X26 = 225
ARM64_REG_X27 = 226 UC_ARM64_REG_X27 = 226
ARM64_REG_X28 = 227 UC_ARM64_REG_X28 = 227
ARM64_REG_V0 = 228 UC_ARM64_REG_V0 = 228
ARM64_REG_V1 = 229 UC_ARM64_REG_V1 = 229
ARM64_REG_V2 = 230 UC_ARM64_REG_V2 = 230
ARM64_REG_V3 = 231 UC_ARM64_REG_V3 = 231
ARM64_REG_V4 = 232 UC_ARM64_REG_V4 = 232
ARM64_REG_V5 = 233 UC_ARM64_REG_V5 = 233
ARM64_REG_V6 = 234 UC_ARM64_REG_V6 = 234
ARM64_REG_V7 = 235 UC_ARM64_REG_V7 = 235
ARM64_REG_V8 = 236 UC_ARM64_REG_V8 = 236
ARM64_REG_V9 = 237 UC_ARM64_REG_V9 = 237
ARM64_REG_V10 = 238 UC_ARM64_REG_V10 = 238
ARM64_REG_V11 = 239 UC_ARM64_REG_V11 = 239
ARM64_REG_V12 = 240 UC_ARM64_REG_V12 = 240
ARM64_REG_V13 = 241 UC_ARM64_REG_V13 = 241
ARM64_REG_V14 = 242 UC_ARM64_REG_V14 = 242
ARM64_REG_V15 = 243 UC_ARM64_REG_V15 = 243
ARM64_REG_V16 = 244 UC_ARM64_REG_V16 = 244
ARM64_REG_V17 = 245 UC_ARM64_REG_V17 = 245
ARM64_REG_V18 = 246 UC_ARM64_REG_V18 = 246
ARM64_REG_V19 = 247 UC_ARM64_REG_V19 = 247
ARM64_REG_V20 = 248 UC_ARM64_REG_V20 = 248
ARM64_REG_V21 = 249 UC_ARM64_REG_V21 = 249
ARM64_REG_V22 = 250 UC_ARM64_REG_V22 = 250
ARM64_REG_V23 = 251 UC_ARM64_REG_V23 = 251
ARM64_REG_V24 = 252 UC_ARM64_REG_V24 = 252
ARM64_REG_V25 = 253 UC_ARM64_REG_V25 = 253
ARM64_REG_V26 = 254 UC_ARM64_REG_V26 = 254
ARM64_REG_V27 = 255 UC_ARM64_REG_V27 = 255
ARM64_REG_V28 = 256 UC_ARM64_REG_V28 = 256
ARM64_REG_V29 = 257 UC_ARM64_REG_V29 = 257
ARM64_REG_V30 = 258 UC_ARM64_REG_V30 = 258
ARM64_REG_V31 = 259 UC_ARM64_REG_V31 = 259
# pseudo registers # pseudo registers
ARM64_REG_PC = 260 UC_ARM64_REG_PC = 260
ARM64_REG_ENDING = 261 UC_ARM64_REG_ENDING = 261
# alias registers # alias registers
ARM64_REG_IP1 = ARM64_REG_X16 UC_ARM64_REG_IP1 = UC_ARM64_REG_X16
ARM64_REG_IP0 = ARM64_REG_X17 UC_ARM64_REG_IP0 = UC_ARM64_REG_X17
ARM64_REG_FP = ARM64_REG_X29 UC_ARM64_REG_FP = UC_ARM64_REG_X29
ARM64_REG_LR = ARM64_REG_X30 UC_ARM64_REG_LR = UC_ARM64_REG_X30

238
bindings/python/unicorn/arm_const.py
View file

@ -2,124 +2,124 @@
# ARM registers # ARM registers
ARM_REG_INVALID = 0 UC_ARM_REG_INVALID = 0
ARM_REG_APSR = 1 UC_ARM_REG_APSR = 1
ARM_REG_APSR_NZCV = 2 UC_ARM_REG_APSR_NZCV = 2
ARM_REG_CPSR = 3 UC_ARM_REG_CPSR = 3
ARM_REG_FPEXC = 4 UC_ARM_REG_FPEXC = 4
ARM_REG_FPINST = 5 UC_ARM_REG_FPINST = 5
ARM_REG_FPSCR = 6 UC_ARM_REG_FPSCR = 6
ARM_REG_FPSCR_NZCV = 7 UC_ARM_REG_FPSCR_NZCV = 7
ARM_REG_FPSID = 8 UC_ARM_REG_FPSID = 8
ARM_REG_ITSTATE = 9 UC_ARM_REG_ITSTATE = 9
ARM_REG_LR = 10 UC_ARM_REG_LR = 10
ARM_REG_PC = 11 UC_ARM_REG_PC = 11
ARM_REG_SP = 12 UC_ARM_REG_SP = 12
ARM_REG_SPSR = 13 UC_ARM_REG_SPSR = 13
ARM_REG_D0 = 14 UC_ARM_REG_D0 = 14
ARM_REG_D1 = 15 UC_ARM_REG_D1 = 15
ARM_REG_D2 = 16 UC_ARM_REG_D2 = 16
ARM_REG_D3 = 17 UC_ARM_REG_D3 = 17
ARM_REG_D4 = 18 UC_ARM_REG_D4 = 18
ARM_REG_D5 = 19 UC_ARM_REG_D5 = 19
ARM_REG_D6 = 20 UC_ARM_REG_D6 = 20
ARM_REG_D7 = 21 UC_ARM_REG_D7 = 21
ARM_REG_D8 = 22 UC_ARM_REG_D8 = 22
ARM_REG_D9 = 23 UC_ARM_REG_D9 = 23
ARM_REG_D10 = 24 UC_ARM_REG_D10 = 24
ARM_REG_D11 = 25 UC_ARM_REG_D11 = 25
ARM_REG_D12 = 26 UC_ARM_REG_D12 = 26
ARM_REG_D13 = 27 UC_ARM_REG_D13 = 27
ARM_REG_D14 = 28 UC_ARM_REG_D14 = 28
ARM_REG_D15 = 29 UC_ARM_REG_D15 = 29
ARM_REG_D16 = 30 UC_ARM_REG_D16 = 30
ARM_REG_D17 = 31 UC_ARM_REG_D17 = 31
ARM_REG_D18 = 32 UC_ARM_REG_D18 = 32
ARM_REG_D19 = 33 UC_ARM_REG_D19 = 33
ARM_REG_D20 = 34 UC_ARM_REG_D20 = 34
ARM_REG_D21 = 35 UC_ARM_REG_D21 = 35
ARM_REG_D22 = 36 UC_ARM_REG_D22 = 36
ARM_REG_D23 = 37 UC_ARM_REG_D23 = 37
ARM_REG_D24 = 38 UC_ARM_REG_D24 = 38
ARM_REG_D25 = 39 UC_ARM_REG_D25 = 39
ARM_REG_D26 = 40 UC_ARM_REG_D26 = 40
ARM_REG_D27 = 41 UC_ARM_REG_D27 = 41
ARM_REG_D28 = 42 UC_ARM_REG_D28 = 42
ARM_REG_D29 = 43 UC_ARM_REG_D29 = 43
ARM_REG_D30 = 44 UC_ARM_REG_D30 = 44
ARM_REG_D31 = 45 UC_ARM_REG_D31 = 45
ARM_REG_FPINST2 = 46 UC_ARM_REG_FPINST2 = 46
ARM_REG_MVFR0 = 47 UC_ARM_REG_MVFR0 = 47
ARM_REG_MVFR1 = 48 UC_ARM_REG_MVFR1 = 48
ARM_REG_MVFR2 = 49 UC_ARM_REG_MVFR2 = 49
ARM_REG_Q0 = 50 UC_ARM_REG_Q0 = 50
ARM_REG_Q1 = 51 UC_ARM_REG_Q1 = 51
ARM_REG_Q2 = 52 UC_ARM_REG_Q2 = 52
ARM_REG_Q3 = 53 UC_ARM_REG_Q3 = 53
ARM_REG_Q4 = 54 UC_ARM_REG_Q4 = 54
ARM_REG_Q5 = 55 UC_ARM_REG_Q5 = 55
ARM_REG_Q6 = 56 UC_ARM_REG_Q6 = 56
ARM_REG_Q7 = 57 UC_ARM_REG_Q7 = 57
ARM_REG_Q8 = 58 UC_ARM_REG_Q8 = 58
ARM_REG_Q9 = 59 UC_ARM_REG_Q9 = 59
ARM_REG_Q10 = 60 UC_ARM_REG_Q10 = 60
ARM_REG_Q11 = 61 UC_ARM_REG_Q11 = 61
ARM_REG_Q12 = 62 UC_ARM_REG_Q12 = 62
ARM_REG_Q13 = 63 UC_ARM_REG_Q13 = 63
ARM_REG_Q14 = 64 UC_ARM_REG_Q14 = 64
ARM_REG_Q15 = 65 UC_ARM_REG_Q15 = 65
ARM_REG_R0 = 66 UC_ARM_REG_R0 = 66
ARM_REG_R1 = 67 UC_ARM_REG_R1 = 67
ARM_REG_R2 = 68 UC_ARM_REG_R2 = 68
ARM_REG_R3 = 69 UC_ARM_REG_R3 = 69
ARM_REG_R4 = 70 UC_ARM_REG_R4 = 70
ARM_REG_R5 = 71 UC_ARM_REG_R5 = 71
ARM_REG_R6 = 72 UC_ARM_REG_R6 = 72
ARM_REG_R7 = 73 UC_ARM_REG_R7 = 73
ARM_REG_R8 = 74 UC_ARM_REG_R8 = 74
ARM_REG_R9 = 75 UC_ARM_REG_R9 = 75
ARM_REG_R10 = 76 UC_ARM_REG_R10 = 76
ARM_REG_R11 = 77 UC_ARM_REG_R11 = 77
ARM_REG_R12 = 78 UC_ARM_REG_R12 = 78
ARM_REG_S0 = 79 UC_ARM_REG_S0 = 79
ARM_REG_S1 = 80 UC_ARM_REG_S1 = 80
ARM_REG_S2 = 81 UC_ARM_REG_S2 = 81
ARM_REG_S3 = 82 UC_ARM_REG_S3 = 82
ARM_REG_S4 = 83 UC_ARM_REG_S4 = 83
ARM_REG_S5 = 84 UC_ARM_REG_S5 = 84
ARM_REG_S6 = 85 UC_ARM_REG_S6 = 85
ARM_REG_S7 = 86 UC_ARM_REG_S7 = 86
ARM_REG_S8 = 87 UC_ARM_REG_S8 = 87
ARM_REG_S9 = 88 UC_ARM_REG_S9 = 88
ARM_REG_S10 = 89 UC_ARM_REG_S10 = 89
ARM_REG_S11 = 90 UC_ARM_REG_S11 = 90
ARM_REG_S12 = 91 UC_ARM_REG_S12 = 91
ARM_REG_S13 = 92 UC_ARM_REG_S13 = 92
ARM_REG_S14 = 93 UC_ARM_REG_S14 = 93
ARM_REG_S15 = 94 UC_ARM_REG_S15 = 94
ARM_REG_S16 = 95 UC_ARM_REG_S16 = 95
ARM_REG_S17 = 96 UC_ARM_REG_S17 = 96
ARM_REG_S18 = 97 UC_ARM_REG_S18 = 97
ARM_REG_S19 = 98 UC_ARM_REG_S19 = 98
ARM_REG_S20 = 99 UC_ARM_REG_S20 = 99
ARM_REG_S21 = 100 UC_ARM_REG_S21 = 100
ARM_REG_S22 = 101 UC_ARM_REG_S22 = 101
ARM_REG_S23 = 102 UC_ARM_REG_S23 = 102
ARM_REG_S24 = 103 UC_ARM_REG_S24 = 103
ARM_REG_S25 = 104 UC_ARM_REG_S25 = 104
ARM_REG_S26 = 105 UC_ARM_REG_S26 = 105
ARM_REG_S27 = 106 UC_ARM_REG_S27 = 106
ARM_REG_S28 = 107 UC_ARM_REG_S28 = 107
ARM_REG_S29 = 108 UC_ARM_REG_S29 = 108
ARM_REG_S30 = 109 UC_ARM_REG_S30 = 109
ARM_REG_S31 = 110 UC_ARM_REG_S31 = 110
ARM_REG_ENDING = 111 UC_ARM_REG_ENDING = 111
# alias registers # alias registers
ARM_REG_R13 = ARM_REG_SP UC_ARM_REG_R13 = UC_ARM_REG_SP
ARM_REG_R14 = ARM_REG_LR UC_ARM_REG_R14 = UC_ARM_REG_LR
ARM_REG_R15 = ARM_REG_PC UC_ARM_REG_R15 = UC_ARM_REG_PC
ARM_REG_SB = ARM_REG_R9 UC_ARM_REG_SB = UC_ARM_REG_R9
ARM_REG_SL = ARM_REG_R10 UC_ARM_REG_SL = UC_ARM_REG_R10
ARM_REG_FP = ARM_REG_R11 UC_ARM_REG_FP = UC_ARM_REG_R11
ARM_REG_IP = ARM_REG_R12 UC_ARM_REG_IP = UC_ARM_REG_R12

40
bindings/python/unicorn/m68k_const.py
View file

@ -2,23 +2,23 @@
# M68K registers # M68K registers
M68K_REG_INVALID = 0 UC_M68K_REG_INVALID = 0
M68K_REG_A0 = 1 UC_M68K_REG_A0 = 1
M68K_REG_A1 = 2 UC_M68K_REG_A1 = 2
M68K_REG_A2 = 3 UC_M68K_REG_A2 = 3
M68K_REG_A3 = 4 UC_M68K_REG_A3 = 4
M68K_REG_A4 = 5 UC_M68K_REG_A4 = 5
M68K_REG_A5 = 6 UC_M68K_REG_A5 = 6
M68K_REG_A6 = 7 UC_M68K_REG_A6 = 7
M68K_REG_A7 = 8 UC_M68K_REG_A7 = 8
M68K_REG_D0 = 9 UC_M68K_REG_D0 = 9
M68K_REG_D1 = 10 UC_M68K_REG_D1 = 10
M68K_REG_D2 = 11 UC_M68K_REG_D2 = 11
M68K_REG_D3 = 12 UC_M68K_REG_D3 = 12
M68K_REG_D4 = 13 UC_M68K_REG_D4 = 13
M68K_REG_D5 = 14 UC_M68K_REG_D5 = 14
M68K_REG_D6 = 15 UC_M68K_REG_D6 = 15
M68K_REG_D7 = 16 UC_M68K_REG_D7 = 16
M68K_REG_SR = 17 UC_M68K_REG_SR = 17
M68K_REG_PC = 18 UC_M68K_REG_PC = 18
M68K_REG_ENDING = 19 UC_M68K_REG_ENDING = 19

358
bindings/python/unicorn/mips_const.py
View file

@ -2,194 +2,194 @@
# MIPS registers # MIPS registers
MIPS_REG_INVALID = 0 UC_MIPS_REG_INVALID = 0
# General purpose registers # General purpose registers
MIPS_REG_PC = 1 UC_MIPS_REG_PC = 1
MIPS_REG_0 = 2 UC_MIPS_REG_0 = 2
MIPS_REG_1 = 3 UC_MIPS_REG_1 = 3
MIPS_REG_2 = 4 UC_MIPS_REG_2 = 4
MIPS_REG_3 = 5 UC_MIPS_REG_3 = 5
MIPS_REG_4 = 6 UC_MIPS_REG_4 = 6
MIPS_REG_5 = 7 UC_MIPS_REG_5 = 7
MIPS_REG_6 = 8 UC_MIPS_REG_6 = 8
MIPS_REG_7 = 9 UC_MIPS_REG_7 = 9
MIPS_REG_8 = 10 UC_MIPS_REG_8 = 10
MIPS_REG_9 = 11 UC_MIPS_REG_9 = 11
MIPS_REG_10 = 12 UC_MIPS_REG_10 = 12
MIPS_REG_11 = 13 UC_MIPS_REG_11 = 13
MIPS_REG_12 = 14 UC_MIPS_REG_12 = 14
MIPS_REG_13 = 15 UC_MIPS_REG_13 = 15
MIPS_REG_14 = 16 UC_MIPS_REG_14 = 16
MIPS_REG_15 = 17 UC_MIPS_REG_15 = 17
MIPS_REG_16 = 18 UC_MIPS_REG_16 = 18
MIPS_REG_17 = 19 UC_MIPS_REG_17 = 19
MIPS_REG_18 = 20 UC_MIPS_REG_18 = 20
MIPS_REG_19 = 21 UC_MIPS_REG_19 = 21
MIPS_REG_20 = 22 UC_MIPS_REG_20 = 22
MIPS_REG_21 = 23 UC_MIPS_REG_21 = 23
MIPS_REG_22 = 24 UC_MIPS_REG_22 = 24
MIPS_REG_23 = 25 UC_MIPS_REG_23 = 25
MIPS_REG_24 = 26 UC_MIPS_REG_24 = 26
MIPS_REG_25 = 27 UC_MIPS_REG_25 = 27
MIPS_REG_26 = 28 UC_MIPS_REG_26 = 28
MIPS_REG_27 = 29 UC_MIPS_REG_27 = 29
MIPS_REG_28 = 30 UC_MIPS_REG_28 = 30
MIPS_REG_29 = 31 UC_MIPS_REG_29 = 31
MIPS_REG_30 = 32 UC_MIPS_REG_30 = 32
MIPS_REG_31 = 33 UC_MIPS_REG_31 = 33
# DSP registers # DSP registers
MIPS_REG_DSPCCOND = 34 UC_MIPS_REG_DSPCCOND = 34
MIPS_REG_DSPCARRY = 35 UC_MIPS_REG_DSPCARRY = 35
MIPS_REG_DSPEFI = 36 UC_MIPS_REG_DSPEFI = 36
MIPS_REG_DSPOUTFLAG = 37 UC_MIPS_REG_DSPOUTFLAG = 37
MIPS_REG_DSPOUTFLAG16_19 = 38 UC_MIPS_REG_DSPOUTFLAG16_19 = 38
MIPS_REG_DSPOUTFLAG20 = 39 UC_MIPS_REG_DSPOUTFLAG20 = 39
MIPS_REG_DSPOUTFLAG21 = 40 UC_MIPS_REG_DSPOUTFLAG21 = 40
MIPS_REG_DSPOUTFLAG22 = 41 UC_MIPS_REG_DSPOUTFLAG22 = 41
MIPS_REG_DSPOUTFLAG23 = 42 UC_MIPS_REG_DSPOUTFLAG23 = 42
MIPS_REG_DSPPOS = 43 UC_MIPS_REG_DSPPOS = 43
MIPS_REG_DSPSCOUNT = 44 UC_MIPS_REG_DSPSCOUNT = 44
# ACC registers # ACC registers
MIPS_REG_AC0 = 45 UC_MIPS_REG_AC0 = 45
MIPS_REG_AC1 = 46 UC_MIPS_REG_AC1 = 46
MIPS_REG_AC2 = 47 UC_MIPS_REG_AC2 = 47
MIPS_REG_AC3 = 48 UC_MIPS_REG_AC3 = 48
# COP registers # COP registers
MIPS_REG_CC0 = 49 UC_MIPS_REG_CC0 = 49
MIPS_REG_CC1 = 50 UC_MIPS_REG_CC1 = 50
MIPS_REG_CC2 = 51 UC_MIPS_REG_CC2 = 51
MIPS_REG_CC3 = 52 UC_MIPS_REG_CC3 = 52
MIPS_REG_CC4 = 53 UC_MIPS_REG_CC4 = 53
MIPS_REG_CC5 = 54 UC_MIPS_REG_CC5 = 54
MIPS_REG_CC6 = 55 UC_MIPS_REG_CC6 = 55
MIPS_REG_CC7 = 56 UC_MIPS_REG_CC7 = 56
# FPU registers # FPU registers
MIPS_REG_F0 = 57 UC_MIPS_REG_F0 = 57
MIPS_REG_F1 = 58 UC_MIPS_REG_F1 = 58
MIPS_REG_F2 = 59 UC_MIPS_REG_F2 = 59
MIPS_REG_F3 = 60 UC_MIPS_REG_F3 = 60
MIPS_REG_F4 = 61 UC_MIPS_REG_F4 = 61
MIPS_REG_F5 = 62 UC_MIPS_REG_F5 = 62
MIPS_REG_F6 = 63 UC_MIPS_REG_F6 = 63
MIPS_REG_F7 = 64 UC_MIPS_REG_F7 = 64
MIPS_REG_F8 = 65 UC_MIPS_REG_F8 = 65
MIPS_REG_F9 = 66 UC_MIPS_REG_F9 = 66
MIPS_REG_F10 = 67 UC_MIPS_REG_F10 = 67
MIPS_REG_F11 = 68 UC_MIPS_REG_F11 = 68
MIPS_REG_F12 = 69 UC_MIPS_REG_F12 = 69
MIPS_REG_F13 = 70 UC_MIPS_REG_F13 = 70
MIPS_REG_F14 = 71 UC_MIPS_REG_F14 = 71
MIPS_REG_F15 = 72 UC_MIPS_REG_F15 = 72
MIPS_REG_F16 = 73 UC_MIPS_REG_F16 = 73
MIPS_REG_F17 = 74 UC_MIPS_REG_F17 = 74
MIPS_REG_F18 = 75 UC_MIPS_REG_F18 = 75
MIPS_REG_F19 = 76 UC_MIPS_REG_F19 = 76
MIPS_REG_F20 = 77 UC_MIPS_REG_F20 = 77
MIPS_REG_F21 = 78 UC_MIPS_REG_F21 = 78
MIPS_REG_F22 = 79 UC_MIPS_REG_F22 = 79
MIPS_REG_F23 = 80 UC_MIPS_REG_F23 = 80
MIPS_REG_F24 = 81 UC_MIPS_REG_F24 = 81
MIPS_REG_F25 = 82 UC_MIPS_REG_F25 = 82
MIPS_REG_F26 = 83 UC_MIPS_REG_F26 = 83
MIPS_REG_F27 = 84 UC_MIPS_REG_F27 = 84
MIPS_REG_F28 = 85 UC_MIPS_REG_F28 = 85
MIPS_REG_F29 = 86 UC_MIPS_REG_F29 = 86
MIPS_REG_F30 = 87 UC_MIPS_REG_F30 = 87
MIPS_REG_F31 = 88 UC_MIPS_REG_F31 = 88
MIPS_REG_FCC0 = 89 UC_MIPS_REG_FCC0 = 89
MIPS_REG_FCC1 = 90 UC_MIPS_REG_FCC1 = 90
MIPS_REG_FCC2 = 91 UC_MIPS_REG_FCC2 = 91
MIPS_REG_FCC3 = 92 UC_MIPS_REG_FCC3 = 92
MIPS_REG_FCC4 = 93 UC_MIPS_REG_FCC4 = 93
MIPS_REG_FCC5 = 94 UC_MIPS_REG_FCC5 = 94
MIPS_REG_FCC6 = 95 UC_MIPS_REG_FCC6 = 95
MIPS_REG_FCC7 = 96 UC_MIPS_REG_FCC7 = 96
# AFPR128 # AFPR128
MIPS_REG_W0 = 97 UC_MIPS_REG_W0 = 97
MIPS_REG_W1 = 98 UC_MIPS_REG_W1 = 98
MIPS_REG_W2 = 99 UC_MIPS_REG_W2 = 99
MIPS_REG_W3 = 100 UC_MIPS_REG_W3 = 100
MIPS_REG_W4 = 101 UC_MIPS_REG_W4 = 101
MIPS_REG_W5 = 102 UC_MIPS_REG_W5 = 102
MIPS_REG_W6 = 103 UC_MIPS_REG_W6 = 103
MIPS_REG_W7 = 104 UC_MIPS_REG_W7 = 104
MIPS_REG_W8 = 105 UC_MIPS_REG_W8 = 105
MIPS_REG_W9 = 106 UC_MIPS_REG_W9 = 106
MIPS_REG_W10 = 107 UC_MIPS_REG_W10 = 107
MIPS_REG_W11 = 108 UC_MIPS_REG_W11 = 108
MIPS_REG_W12 = 109 UC_MIPS_REG_W12 = 109
MIPS_REG_W13 = 110 UC_MIPS_REG_W13 = 110
MIPS_REG_W14 = 111 UC_MIPS_REG_W14 = 111
MIPS_REG_W15 = 112 UC_MIPS_REG_W15 = 112
MIPS_REG_W16 = 113 UC_MIPS_REG_W16 = 113
MIPS_REG_W17 = 114 UC_MIPS_REG_W17 = 114
MIPS_REG_W18 = 115 UC_MIPS_REG_W18 = 115
MIPS_REG_W19 = 116 UC_MIPS_REG_W19 = 116
MIPS_REG_W20 = 117 UC_MIPS_REG_W20 = 117
MIPS_REG_W21 = 118 UC_MIPS_REG_W21 = 118
MIPS_REG_W22 = 119 UC_MIPS_REG_W22 = 119
MIPS_REG_W23 = 120 UC_MIPS_REG_W23 = 120
MIPS_REG_W24 = 121 UC_MIPS_REG_W24 = 121
MIPS_REG_W25 = 122 UC_MIPS_REG_W25 = 122
MIPS_REG_W26 = 123 UC_MIPS_REG_W26 = 123
MIPS_REG_W27 = 124 UC_MIPS_REG_W27 = 124
MIPS_REG_W28 = 125 UC_MIPS_REG_W28 = 125
MIPS_REG_W29 = 126 UC_MIPS_REG_W29 = 126
MIPS_REG_W30 = 127 UC_MIPS_REG_W30 = 127
MIPS_REG_W31 = 128 UC_MIPS_REG_W31 = 128
MIPS_REG_HI = 129 UC_MIPS_REG_HI = 129
MIPS_REG_LO = 130 UC_MIPS_REG_LO = 130
MIPS_REG_P0 = 131 UC_MIPS_REG_P0 = 131
MIPS_REG_P1 = 132 UC_MIPS_REG_P1 = 132
MIPS_REG_P2 = 133 UC_MIPS_REG_P2 = 133
MIPS_REG_MPL0 = 134 UC_MIPS_REG_MPL0 = 134
MIPS_REG_MPL1 = 135 UC_MIPS_REG_MPL1 = 135
MIPS_REG_MPL2 = 136 UC_MIPS_REG_MPL2 = 136
MIPS_REG_ENDING = 137 UC_MIPS_REG_ENDING = 137
MIPS_REG_ZERO = MIPS_REG_0 UC_MIPS_REG_ZERO = UC_MIPS_REG_0
MIPS_REG_AT = MIPS_REG_1 UC_MIPS_REG_AT = UC_MIPS_REG_1
MIPS_REG_V0 = MIPS_REG_2 UC_MIPS_REG_V0 = UC_MIPS_REG_2
MIPS_REG_V1 = MIPS_REG_3 UC_MIPS_REG_V1 = UC_MIPS_REG_3
MIPS_REG_A0 = MIPS_REG_4 UC_MIPS_REG_A0 = UC_MIPS_REG_4
MIPS_REG_A1 = MIPS_REG_5 UC_MIPS_REG_A1 = UC_MIPS_REG_5
MIPS_REG_A2 = MIPS_REG_6 UC_MIPS_REG_A2 = UC_MIPS_REG_6
MIPS_REG_A3 = MIPS_REG_7 UC_MIPS_REG_A3 = UC_MIPS_REG_7
MIPS_REG_T0 = MIPS_REG_8 UC_MIPS_REG_T0 = UC_MIPS_REG_8
MIPS_REG_T1 = MIPS_REG_9 UC_MIPS_REG_T1 = UC_MIPS_REG_9
MIPS_REG_T2 = MIPS_REG_10 UC_MIPS_REG_T2 = UC_MIPS_REG_10
MIPS_REG_T3 = MIPS_REG_11 UC_MIPS_REG_T3 = UC_MIPS_REG_11
MIPS_REG_T4 = MIPS_REG_12 UC_MIPS_REG_T4 = UC_MIPS_REG_12
MIPS_REG_T5 = MIPS_REG_13 UC_MIPS_REG_T5 = UC_MIPS_REG_13
MIPS_REG_T6 = MIPS_REG_14 UC_MIPS_REG_T6 = UC_MIPS_REG_14
MIPS_REG_T7 = MIPS_REG_15 UC_MIPS_REG_T7 = UC_MIPS_REG_15
MIPS_REG_S0 = MIPS_REG_16 UC_MIPS_REG_S0 = UC_MIPS_REG_16
MIPS_REG_S1 = MIPS_REG_17 UC_MIPS_REG_S1 = UC_MIPS_REG_17
MIPS_REG_S2 = MIPS_REG_18 UC_MIPS_REG_S2 = UC_MIPS_REG_18
MIPS_REG_S3 = MIPS_REG_19 UC_MIPS_REG_S3 = UC_MIPS_REG_19
MIPS_REG_S4 = MIPS_REG_20 UC_MIPS_REG_S4 = UC_MIPS_REG_20
MIPS_REG_S5 = MIPS_REG_21 UC_MIPS_REG_S5 = UC_MIPS_REG_21
MIPS_REG_S6 = MIPS_REG_22 UC_MIPS_REG_S6 = UC_MIPS_REG_22
MIPS_REG_S7 = MIPS_REG_23 UC_MIPS_REG_S7 = UC_MIPS_REG_23
MIPS_REG_T8 = MIPS_REG_24 UC_MIPS_REG_T8 = UC_MIPS_REG_24
MIPS_REG_T9 = MIPS_REG_25 UC_MIPS_REG_T9 = UC_MIPS_REG_25
MIPS_REG_K0 = MIPS_REG_26 UC_MIPS_REG_K0 = UC_MIPS_REG_26
MIPS_REG_K1 = MIPS_REG_27 UC_MIPS_REG_K1 = UC_MIPS_REG_27
MIPS_REG_GP = MIPS_REG_28 UC_MIPS_REG_GP = UC_MIPS_REG_28
MIPS_REG_SP = MIPS_REG_29 UC_MIPS_REG_SP = UC_MIPS_REG_29
MIPS_REG_FP = MIPS_REG_30 UC_MIPS_REG_FP = UC_MIPS_REG_30
MIPS_REG_S8 = MIPS_REG_30 UC_MIPS_REG_S8 = UC_MIPS_REG_30
MIPS_REG_RA = MIPS_REG_31 UC_MIPS_REG_RA = UC_MIPS_REG_31
MIPS_REG_HI0 = MIPS_REG_AC0 UC_MIPS_REG_HI0 = UC_MIPS_REG_AC0
MIPS_REG_HI1 = MIPS_REG_AC1 UC_MIPS_REG_HI1 = UC_MIPS_REG_AC1
MIPS_REG_HI2 = MIPS_REG_AC2 UC_MIPS_REG_HI2 = UC_MIPS_REG_AC2
MIPS_REG_HI3 = MIPS_REG_AC3 UC_MIPS_REG_HI3 = UC_MIPS_REG_AC3
MIPS_REG_LO0 = MIPS_REG_HI0 UC_MIPS_REG_LO0 = UC_MIPS_REG_HI0
MIPS_REG_LO1 = MIPS_REG_HI1 UC_MIPS_REG_LO1 = UC_MIPS_REG_HI1
MIPS_REG_LO2 = MIPS_REG_HI2 UC_MIPS_REG_LO2 = UC_MIPS_REG_HI2
MIPS_REG_LO3 = MIPS_REG_HI3 UC_MIPS_REG_LO3 = UC_MIPS_REG_HI3

184
bindings/python/unicorn/sparc_const.py
View file

@ -2,95 +2,95 @@
# SPARC registers # SPARC registers
SPARC_REG_INVALID = 0 UC_SPARC_REG_INVALID = 0
SPARC_REG_F0 = 1 UC_SPARC_REG_F0 = 1
SPARC_REG_F1 = 2 UC_SPARC_REG_F1 = 2
SPARC_REG_F2 = 3 UC_SPARC_REG_F2 = 3
SPARC_REG_F3 = 4 UC_SPARC_REG_F3 = 4
SPARC_REG_F4 = 5 UC_SPARC_REG_F4 = 5
SPARC_REG_F5 = 6 UC_SPARC_REG_F5 = 6
SPARC_REG_F6 = 7 UC_SPARC_REG_F6 = 7
SPARC_REG_F7 = 8 UC_SPARC_REG_F7 = 8
SPARC_REG_F8 = 9 UC_SPARC_REG_F8 = 9
SPARC_REG_F9 = 10 UC_SPARC_REG_F9 = 10
SPARC_REG_F10 = 11 UC_SPARC_REG_F10 = 11
SPARC_REG_F11 = 12 UC_SPARC_REG_F11 = 12
SPARC_REG_F12 = 13 UC_SPARC_REG_F12 = 13
SPARC_REG_F13 = 14 UC_SPARC_REG_F13 = 14
SPARC_REG_F14 = 15 UC_SPARC_REG_F14 = 15
SPARC_REG_F15 = 16 UC_SPARC_REG_F15 = 16
SPARC_REG_F16 = 17 UC_SPARC_REG_F16 = 17
SPARC_REG_F17 = 18 UC_SPARC_REG_F17 = 18
SPARC_REG_F18 = 19 UC_SPARC_REG_F18 = 19
SPARC_REG_F19 = 20 UC_SPARC_REG_F19 = 20
SPARC_REG_F20 = 21 UC_SPARC_REG_F20 = 21
SPARC_REG_F21 = 22 UC_SPARC_REG_F21 = 22
SPARC_REG_F22 = 23 UC_SPARC_REG_F22 = 23
SPARC_REG_F23 = 24 UC_SPARC_REG_F23 = 24
SPARC_REG_F24 = 25 UC_SPARC_REG_F24 = 25
SPARC_REG_F25 = 26 UC_SPARC_REG_F25 = 26
SPARC_REG_F26 = 27 UC_SPARC_REG_F26 = 27
SPARC_REG_F27 = 28 UC_SPARC_REG_F27 = 28
SPARC_REG_F28 = 29 UC_SPARC_REG_F28 = 29
SPARC_REG_F29 = 30 UC_SPARC_REG_F29 = 30
SPARC_REG_F30 = 31 UC_SPARC_REG_F30 = 31
SPARC_REG_F31 = 32 UC_SPARC_REG_F31 = 32
SPARC_REG_F32 = 33 UC_SPARC_REG_F32 = 33
SPARC_REG_F34 = 34 UC_SPARC_REG_F34 = 34
SPARC_REG_F36 = 35 UC_SPARC_REG_F36 = 35
SPARC_REG_F38 = 36 UC_SPARC_REG_F38 = 36
SPARC_REG_F40 = 37 UC_SPARC_REG_F40 = 37
SPARC_REG_F42 = 38 UC_SPARC_REG_F42 = 38
SPARC_REG_F44 = 39 UC_SPARC_REG_F44 = 39
SPARC_REG_F46 = 40 UC_SPARC_REG_F46 = 40
SPARC_REG_F48 = 41 UC_SPARC_REG_F48 = 41
SPARC_REG_F50 = 42 UC_SPARC_REG_F50 = 42
SPARC_REG_F52 = 43 UC_SPARC_REG_F52 = 43
SPARC_REG_F54 = 44 UC_SPARC_REG_F54 = 44
SPARC_REG_F56 = 45 UC_SPARC_REG_F56 = 45
SPARC_REG_F58 = 46 UC_SPARC_REG_F58 = 46
SPARC_REG_F60 = 47 UC_SPARC_REG_F60 = 47
SPARC_REG_F62 = 48 UC_SPARC_REG_F62 = 48
SPARC_REG_FCC0 = 49 UC_SPARC_REG_FCC0 = 49
SPARC_REG_FCC1 = 50 UC_SPARC_REG_FCC1 = 50
SPARC_REG_FCC2 = 51 UC_SPARC_REG_FCC2 = 51
SPARC_REG_FCC3 = 52 UC_SPARC_REG_FCC3 = 52
SPARC_REG_FP = 53 UC_SPARC_REG_FP = 53
SPARC_REG_G0 = 54 UC_SPARC_REG_G0 = 54
SPARC_REG_G1 = 55 UC_SPARC_REG_G1 = 55
SPARC_REG_G2 = 56 UC_SPARC_REG_G2 = 56
SPARC_REG_G3 = 57 UC_SPARC_REG_G3 = 57
SPARC_REG_G4 = 58 UC_SPARC_REG_G4 = 58
SPARC_REG_G5 = 59 UC_SPARC_REG_G5 = 59
SPARC_REG_G6 = 60 UC_SPARC_REG_G6 = 60
SPARC_REG_G7 = 61 UC_SPARC_REG_G7 = 61
SPARC_REG_I0 = 62 UC_SPARC_REG_I0 = 62
SPARC_REG_I1 = 63 UC_SPARC_REG_I1 = 63
SPARC_REG_I2 = 64 UC_SPARC_REG_I2 = 64
SPARC_REG_I3 = 65 UC_SPARC_REG_I3 = 65
SPARC_REG_I4 = 66 UC_SPARC_REG_I4 = 66
SPARC_REG_I5 = 67 UC_SPARC_REG_I5 = 67
SPARC_REG_I7 = 68 UC_SPARC_REG_I7 = 68
SPARC_REG_ICC = 69 UC_SPARC_REG_ICC = 69
SPARC_REG_L0 = 70 UC_SPARC_REG_L0 = 70
SPARC_REG_L1 = 71 UC_SPARC_REG_L1 = 71
SPARC_REG_L2 = 72 UC_SPARC_REG_L2 = 72
SPARC_REG_L3 = 73 UC_SPARC_REG_L3 = 73
SPARC_REG_L4 = 74 UC_SPARC_REG_L4 = 74
SPARC_REG_L5 = 75 UC_SPARC_REG_L5 = 75
SPARC_REG_L6 = 76 UC_SPARC_REG_L6 = 76
SPARC_REG_L7 = 77 UC_SPARC_REG_L7 = 77
SPARC_REG_O0 = 78 UC_SPARC_REG_O0 = 78
SPARC_REG_O1 = 79 UC_SPARC_REG_O1 = 79
SPARC_REG_O2 = 80 UC_SPARC_REG_O2 = 80
SPARC_REG_O3 = 81 UC_SPARC_REG_O3 = 81
SPARC_REG_O4 = 82 UC_SPARC_REG_O4 = 82
SPARC_REG_O5 = 83 UC_SPARC_REG_O5 = 83
SPARC_REG_O7 = 84 UC_SPARC_REG_O7 = 84
SPARC_REG_SP = 85 UC_SPARC_REG_SP = 85
SPARC_REG_Y = 86 UC_SPARC_REG_Y = 86
SPARC_REG_XCC = 87 UC_SPARC_REG_XCC = 87
SPARC_REG_PC = 88 UC_SPARC_REG_PC = 88
SPARC_REG_ENDING = 89 UC_SPARC_REG_ENDING = 89
SPARC_REG_O6 = SPARC_REG_SP UC_SPARC_REG_O6 = UC_SPARC_REG_SP
SPARC_REG_I6 = SPARC_REG_FP UC_SPARC_REG_I6 = UC_SPARC_REG_FP

3164
bindings/python/unicorn/x86_const.py
View file

File diff suppressed because it is too large Load diff

1
include/uc_priv.h
View file

@ -146,6 +146,7 @@ struct uc_struct {
int hook_intr_idx; // for handling interrupt int hook_intr_idx; // for handling interrupt
int hook_out_idx; // for handling OUT instruction (X86) int hook_out_idx; // for handling OUT instruction (X86)
int hook_in_idx; // for handling IN instruction (X86) int hook_in_idx; // for handling IN instruction (X86)
int hook_syscall_idx; // for handling SYSCALL/SYSENTER (X86)
bool init_tcg; // already initialized local TCGv variables? bool init_tcg; // already initialized local TCGv variables?

242
include/unicorn/arm.h
View file

@ -13,131 +13,131 @@ extern "C" {
#endif #endif
//> ARM registers //> ARM registers
typedef enum arm_reg { typedef enum uc_arm_reg {
ARM_REG_INVALID = 0, UC_ARM_REG_INVALID = 0,
ARM_REG_APSR, UC_ARM_REG_APSR,
ARM_REG_APSR_NZCV, UC_ARM_REG_APSR_NZCV,
ARM_REG_CPSR, UC_ARM_REG_CPSR,
ARM_REG_FPEXC, UC_ARM_REG_FPEXC,
ARM_REG_FPINST, UC_ARM_REG_FPINST,
ARM_REG_FPSCR, UC_ARM_REG_FPSCR,
ARM_REG_FPSCR_NZCV, UC_ARM_REG_FPSCR_NZCV,
ARM_REG_FPSID, UC_ARM_REG_FPSID,
ARM_REG_ITSTATE, UC_ARM_REG_ITSTATE,
ARM_REG_LR, UC_ARM_REG_LR,
ARM_REG_PC, UC_ARM_REG_PC,
ARM_REG_SP, UC_ARM_REG_SP,
ARM_REG_SPSR, UC_ARM_REG_SPSR,
ARM_REG_D0, UC_ARM_REG_D0,
ARM_REG_D1, UC_ARM_REG_D1,
ARM_REG_D2, UC_ARM_REG_D2,
ARM_REG_D3, UC_ARM_REG_D3,
ARM_REG_D4, UC_ARM_REG_D4,
ARM_REG_D5, UC_ARM_REG_D5,
ARM_REG_D6, UC_ARM_REG_D6,
ARM_REG_D7, UC_ARM_REG_D7,
ARM_REG_D8, UC_ARM_REG_D8,
ARM_REG_D9, UC_ARM_REG_D9,
ARM_REG_D10, UC_ARM_REG_D10,
ARM_REG_D11, UC_ARM_REG_D11,
ARM_REG_D12, UC_ARM_REG_D12,
ARM_REG_D13, UC_ARM_REG_D13,
ARM_REG_D14, UC_ARM_REG_D14,
ARM_REG_D15, UC_ARM_REG_D15,
ARM_REG_D16, UC_ARM_REG_D16,
ARM_REG_D17, UC_ARM_REG_D17,
ARM_REG_D18, UC_ARM_REG_D18,
ARM_REG_D19, UC_ARM_REG_D19,
ARM_REG_D20, UC_ARM_REG_D20,
ARM_REG_D21, UC_ARM_REG_D21,
ARM_REG_D22, UC_ARM_REG_D22,
ARM_REG_D23, UC_ARM_REG_D23,
ARM_REG_D24, UC_ARM_REG_D24,
ARM_REG_D25, UC_ARM_REG_D25,
ARM_REG_D26, UC_ARM_REG_D26,
ARM_REG_D27, UC_ARM_REG_D27,
ARM_REG_D28, UC_ARM_REG_D28,
ARM_REG_D29, UC_ARM_REG_D29,
ARM_REG_D30, UC_ARM_REG_D30,
ARM_REG_D31, UC_ARM_REG_D31,
ARM_REG_FPINST2, UC_ARM_REG_FPINST2,
ARM_REG_MVFR0, UC_ARM_REG_MVFR0,
ARM_REG_MVFR1, UC_ARM_REG_MVFR1,
ARM_REG_MVFR2, UC_ARM_REG_MVFR2,
ARM_REG_Q0, UC_ARM_REG_Q0,
ARM_REG_Q1, UC_ARM_REG_Q1,
ARM_REG_Q2, UC_ARM_REG_Q2,
ARM_REG_Q3, UC_ARM_REG_Q3,
ARM_REG_Q4, UC_ARM_REG_Q4,
ARM_REG_Q5, UC_ARM_REG_Q5,
ARM_REG_Q6, UC_ARM_REG_Q6,
ARM_REG_Q7, UC_ARM_REG_Q7,
ARM_REG_Q8, UC_ARM_REG_Q8,
ARM_REG_Q9, UC_ARM_REG_Q9,
ARM_REG_Q10, UC_ARM_REG_Q10,
ARM_REG_Q11, UC_ARM_REG_Q11,
ARM_REG_Q12, UC_ARM_REG_Q12,
ARM_REG_Q13, UC_ARM_REG_Q13,
ARM_REG_Q14, UC_ARM_REG_Q14,
ARM_REG_Q15, UC_ARM_REG_Q15,
ARM_REG_R0, UC_ARM_REG_R0,
ARM_REG_R1, UC_ARM_REG_R1,
ARM_REG_R2, UC_ARM_REG_R2,
ARM_REG_R3, UC_ARM_REG_R3,
ARM_REG_R4, UC_ARM_REG_R4,
ARM_REG_R5, UC_ARM_REG_R5,
ARM_REG_R6, UC_ARM_REG_R6,
ARM_REG_R7, UC_ARM_REG_R7,
ARM_REG_R8, UC_ARM_REG_R8,
ARM_REG_R9, UC_ARM_REG_R9,
ARM_REG_R10, UC_ARM_REG_R10,
ARM_REG_R11, UC_ARM_REG_R11,
ARM_REG_R12, UC_ARM_REG_R12,
ARM_REG_S0, UC_ARM_REG_S0,
ARM_REG_S1, UC_ARM_REG_S1,
ARM_REG_S2, UC_ARM_REG_S2,
ARM_REG_S3, UC_ARM_REG_S3,
ARM_REG_S4, UC_ARM_REG_S4,
ARM_REG_S5, UC_ARM_REG_S5,
ARM_REG_S6, UC_ARM_REG_S6,
ARM_REG_S7, UC_ARM_REG_S7,
ARM_REG_S8, UC_ARM_REG_S8,
ARM_REG_S9, UC_ARM_REG_S9,
ARM_REG_S10, UC_ARM_REG_S10,
ARM_REG_S11, UC_ARM_REG_S11,
ARM_REG_S12, UC_ARM_REG_S12,
ARM_REG_S13, UC_ARM_REG_S13,
ARM_REG_S14, UC_ARM_REG_S14,
ARM_REG_S15, UC_ARM_REG_S15,
ARM_REG_S16, UC_ARM_REG_S16,
ARM_REG_S17, UC_ARM_REG_S17,
ARM_REG_S18, UC_ARM_REG_S18,
ARM_REG_S19, UC_ARM_REG_S19,
ARM_REG_S20, UC_ARM_REG_S20,
ARM_REG_S21, UC_ARM_REG_S21,
ARM_REG_S22, UC_ARM_REG_S22,
ARM_REG_S23, UC_ARM_REG_S23,
ARM_REG_S24, UC_ARM_REG_S24,
ARM_REG_S25, UC_ARM_REG_S25,
ARM_REG_S26, UC_ARM_REG_S26,
ARM_REG_S27, UC_ARM_REG_S27,
ARM_REG_S28, UC_ARM_REG_S28,
ARM_REG_S29, UC_ARM_REG_S29,
ARM_REG_S30, UC_ARM_REG_S30,
ARM_REG_S31, UC_ARM_REG_S31,
ARM_REG_ENDING, // <-- mark the end of the list or registers UC_ARM_REG_ENDING, // <-- mark the end of the list or registers
//> alias registers //> alias registers
ARM_REG_R13 = ARM_REG_SP, UC_ARM_REG_R13 = UC_ARM_REG_SP,
ARM_REG_R14 = ARM_REG_LR, UC_ARM_REG_R14 = UC_ARM_REG_LR,
ARM_REG_R15 = ARM_REG_PC, UC_ARM_REG_R15 = UC_ARM_REG_PC,
ARM_REG_SB = ARM_REG_R9, UC_ARM_REG_SB = UC_ARM_REG_R9,
ARM_REG_SL = ARM_REG_R10, UC_ARM_REG_SL = UC_ARM_REG_R10,
ARM_REG_FP = ARM_REG_R11, UC_ARM_REG_FP = UC_ARM_REG_R11,
ARM_REG_IP = ARM_REG_R12, UC_ARM_REG_IP = UC_ARM_REG_R12,
} arm_reg; } uc_arm_reg;
#ifdef __cplusplus #ifdef __cplusplus
} }

536
include/unicorn/arm64.h
View file

@ -13,282 +13,282 @@ extern "C" {
#endif #endif
//> ARM64 registers //> ARM64 registers
typedef enum arm64_reg { typedef enum uc_arm64_reg {
ARM64_REG_INVALID = 0, UC_ARM64_REG_INVALID = 0,
ARM64_REG_X29, UC_ARM64_REG_X29,
ARM64_REG_X30, UC_ARM64_REG_X30,
ARM64_REG_NZCV, UC_ARM64_REG_NZCV,
ARM64_REG_SP, UC_ARM64_REG_SP,
ARM64_REG_WSP, UC_ARM64_REG_WSP,
ARM64_REG_WZR, UC_ARM64_REG_WZR,
ARM64_REG_XZR, UC_ARM64_REG_XZR,
ARM64_REG_B0, UC_ARM64_REG_B0,
ARM64_REG_B1, UC_ARM64_REG_B1,
ARM64_REG_B2, UC_ARM64_REG_B2,
ARM64_REG_B3, UC_ARM64_REG_B3,
ARM64_REG_B4, UC_ARM64_REG_B4,
ARM64_REG_B5, UC_ARM64_REG_B5,
ARM64_REG_B6, UC_ARM64_REG_B6,
ARM64_REG_B7, UC_ARM64_REG_B7,
ARM64_REG_B8, UC_ARM64_REG_B8,
ARM64_REG_B9, UC_ARM64_REG_B9,
ARM64_REG_B10, UC_ARM64_REG_B10,
ARM64_REG_B11, UC_ARM64_REG_B11,
ARM64_REG_B12, UC_ARM64_REG_B12,
ARM64_REG_B13, UC_ARM64_REG_B13,
ARM64_REG_B14, UC_ARM64_REG_B14,
ARM64_REG_B15, UC_ARM64_REG_B15,
ARM64_REG_B16, UC_ARM64_REG_B16,
ARM64_REG_B17, UC_ARM64_REG_B17,
ARM64_REG_B18, UC_ARM64_REG_B18,
ARM64_REG_B19, UC_ARM64_REG_B19,
ARM64_REG_B20, UC_ARM64_REG_B20,
ARM64_REG_B21, UC_ARM64_REG_B21,
ARM64_REG_B22, UC_ARM64_REG_B22,
ARM64_REG_B23, UC_ARM64_REG_B23,
ARM64_REG_B24, UC_ARM64_REG_B24,
ARM64_REG_B25, UC_ARM64_REG_B25,
ARM64_REG_B26, UC_ARM64_REG_B26,
ARM64_REG_B27, UC_ARM64_REG_B27,
ARM64_REG_B28, UC_ARM64_REG_B28,
ARM64_REG_B29, UC_ARM64_REG_B29,
ARM64_REG_B30, UC_ARM64_REG_B30,
ARM64_REG_B31, UC_ARM64_REG_B31,
ARM64_REG_D0, UC_ARM64_REG_D0,
ARM64_REG_D1, UC_ARM64_REG_D1,
ARM64_REG_D2, UC_ARM64_REG_D2,
ARM64_REG_D3, UC_ARM64_REG_D3,
ARM64_REG_D4, UC_ARM64_REG_D4,
ARM64_REG_D5, UC_ARM64_REG_D5,
ARM64_REG_D6, UC_ARM64_REG_D6,
ARM64_REG_D7, UC_ARM64_REG_D7,
ARM64_REG_D8, UC_ARM64_REG_D8,
ARM64_REG_D9, UC_ARM64_REG_D9,
ARM64_REG_D10, UC_ARM64_REG_D10,
ARM64_REG_D11, UC_ARM64_REG_D11,
ARM64_REG_D12, UC_ARM64_REG_D12,
ARM64_REG_D13, UC_ARM64_REG_D13,
ARM64_REG_D14, UC_ARM64_REG_D14,
ARM64_REG_D15, UC_ARM64_REG_D15,
ARM64_REG_D16, UC_ARM64_REG_D16,
ARM64_REG_D17, UC_ARM64_REG_D17,
ARM64_REG_D18, UC_ARM64_REG_D18,
ARM64_REG_D19, UC_ARM64_REG_D19,
ARM64_REG_D20, UC_ARM64_REG_D20,
ARM64_REG_D21, UC_ARM64_REG_D21,
ARM64_REG_D22, UC_ARM64_REG_D22,
ARM64_REG_D23, UC_ARM64_REG_D23,
ARM64_REG_D24, UC_ARM64_REG_D24,
ARM64_REG_D25, UC_ARM64_REG_D25,
ARM64_REG_D26, UC_ARM64_REG_D26,
ARM64_REG_D27, UC_ARM64_REG_D27,
ARM64_REG_D28, UC_ARM64_REG_D28,
ARM64_REG_D29, UC_ARM64_REG_D29,
ARM64_REG_D30, UC_ARM64_REG_D30,
ARM64_REG_D31, UC_ARM64_REG_D31,
ARM64_REG_H0, UC_ARM64_REG_H0,
ARM64_REG_H1, UC_ARM64_REG_H1,
ARM64_REG_H2, UC_ARM64_REG_H2,
ARM64_REG_H3, UC_ARM64_REG_H3,
ARM64_REG_H4, UC_ARM64_REG_H4,
ARM64_REG_H5, UC_ARM64_REG_H5,
ARM64_REG_H6, UC_ARM64_REG_H6,
ARM64_REG_H7, UC_ARM64_REG_H7,
ARM64_REG_H8, UC_ARM64_REG_H8,
ARM64_REG_H9, UC_ARM64_REG_H9,
ARM64_REG_H10, UC_ARM64_REG_H10,
ARM64_REG_H11, UC_ARM64_REG_H11,
ARM64_REG_H12, UC_ARM64_REG_H12,
ARM64_REG_H13, UC_ARM64_REG_H13,
ARM64_REG_H14, UC_ARM64_REG_H14,
ARM64_REG_H15, UC_ARM64_REG_H15,
ARM64_REG_H16, UC_ARM64_REG_H16,
ARM64_REG_H17, UC_ARM64_REG_H17,
ARM64_REG_H18, UC_ARM64_REG_H18,
ARM64_REG_H19, UC_ARM64_REG_H19,
ARM64_REG_H20, UC_ARM64_REG_H20,
ARM64_REG_H21, UC_ARM64_REG_H21,
ARM64_REG_H22, UC_ARM64_REG_H22,
ARM64_REG_H23, UC_ARM64_REG_H23,
ARM64_REG_H24, UC_ARM64_REG_H24,
ARM64_REG_H25, UC_ARM64_REG_H25,
ARM64_REG_H26, UC_ARM64_REG_H26,
ARM64_REG_H27, UC_ARM64_REG_H27,
ARM64_REG_H28, UC_ARM64_REG_H28,
ARM64_REG_H29, UC_ARM64_REG_H29,
ARM64_REG_H30, UC_ARM64_REG_H30,
ARM64_REG_H31, UC_ARM64_REG_H31,
ARM64_REG_Q0, UC_ARM64_REG_Q0,
ARM64_REG_Q1, UC_ARM64_REG_Q1,
ARM64_REG_Q2, UC_ARM64_REG_Q2,
ARM64_REG_Q3, UC_ARM64_REG_Q3,
ARM64_REG_Q4, UC_ARM64_REG_Q4,
ARM64_REG_Q5, UC_ARM64_REG_Q5,
ARM64_REG_Q6, UC_ARM64_REG_Q6,
ARM64_REG_Q7, UC_ARM64_REG_Q7,
ARM64_REG_Q8, UC_ARM64_REG_Q8,
ARM64_REG_Q9, UC_ARM64_REG_Q9,
ARM64_REG_Q10, UC_ARM64_REG_Q10,
ARM64_REG_Q11, UC_ARM64_REG_Q11,
ARM64_REG_Q12, UC_ARM64_REG_Q12,
ARM64_REG_Q13, UC_ARM64_REG_Q13,
ARM64_REG_Q14, UC_ARM64_REG_Q14,
ARM64_REG_Q15, UC_ARM64_REG_Q15,
ARM64_REG_Q16, UC_ARM64_REG_Q16,
ARM64_REG_Q17, UC_ARM64_REG_Q17,
ARM64_REG_Q18, UC_ARM64_REG_Q18,
ARM64_REG_Q19, UC_ARM64_REG_Q19,
ARM64_REG_Q20, UC_ARM64_REG_Q20,
ARM64_REG_Q21, UC_ARM64_REG_Q21,
ARM64_REG_Q22, UC_ARM64_REG_Q22,
ARM64_REG_Q23, UC_ARM64_REG_Q23,
ARM64_REG_Q24, UC_ARM64_REG_Q24,
ARM64_REG_Q25, UC_ARM64_REG_Q25,
ARM64_REG_Q26, UC_ARM64_REG_Q26,
ARM64_REG_Q27, UC_ARM64_REG_Q27,
ARM64_REG_Q28, UC_ARM64_REG_Q28,
ARM64_REG_Q29, UC_ARM64_REG_Q29,
ARM64_REG_Q30, UC_ARM64_REG_Q30,
ARM64_REG_Q31, UC_ARM64_REG_Q31,
ARM64_REG_S0, UC_ARM64_REG_S0,
ARM64_REG_S1, UC_ARM64_REG_S1,
ARM64_REG_S2, UC_ARM64_REG_S2,
ARM64_REG_S3, UC_ARM64_REG_S3,
ARM64_REG_S4, UC_ARM64_REG_S4,
ARM64_REG_S5, UC_ARM64_REG_S5,
ARM64_REG_S6, UC_ARM64_REG_S6,
ARM64_REG_S7, UC_ARM64_REG_S7,
ARM64_REG_S8, UC_ARM64_REG_S8,
ARM64_REG_S9, UC_ARM64_REG_S9,
ARM64_REG_S10, UC_ARM64_REG_S10,
ARM64_REG_S11, UC_ARM64_REG_S11,
ARM64_REG_S12, UC_ARM64_REG_S12,
ARM64_REG_S13, UC_ARM64_REG_S13,
ARM64_REG_S14, UC_ARM64_REG_S14,
ARM64_REG_S15, UC_ARM64_REG_S15,
ARM64_REG_S16, UC_ARM64_REG_S16,
ARM64_REG_S17, UC_ARM64_REG_S17,
ARM64_REG_S18, UC_ARM64_REG_S18,
ARM64_REG_S19, UC_ARM64_REG_S19,
ARM64_REG_S20, UC_ARM64_REG_S20,
ARM64_REG_S21, UC_ARM64_REG_S21,
ARM64_REG_S22, UC_ARM64_REG_S22,
ARM64_REG_S23, UC_ARM64_REG_S23,
ARM64_REG_S24, UC_ARM64_REG_S24,
ARM64_REG_S25, UC_ARM64_REG_S25,
ARM64_REG_S26, UC_ARM64_REG_S26,
ARM64_REG_S27, UC_ARM64_REG_S27,
ARM64_REG_S28, UC_ARM64_REG_S28,
ARM64_REG_S29, UC_ARM64_REG_S29,
ARM64_REG_S30, UC_ARM64_REG_S30,
ARM64_REG_S31, UC_ARM64_REG_S31,
ARM64_REG_W0, UC_ARM64_REG_W0,
ARM64_REG_W1, UC_ARM64_REG_W1,
ARM64_REG_W2, UC_ARM64_REG_W2,
ARM64_REG_W3, UC_ARM64_REG_W3,
ARM64_REG_W4, UC_ARM64_REG_W4,
ARM64_REG_W5, UC_ARM64_REG_W5,
ARM64_REG_W6, UC_ARM64_REG_W6,
ARM64_REG_W7, UC_ARM64_REG_W7,
ARM64_REG_W8, UC_ARM64_REG_W8,
ARM64_REG_W9, UC_ARM64_REG_W9,
ARM64_REG_W10, UC_ARM64_REG_W10,
ARM64_REG_W11, UC_ARM64_REG_W11,
ARM64_REG_W12, UC_ARM64_REG_W12,
ARM64_REG_W13, UC_ARM64_REG_W13,
ARM64_REG_W14, UC_ARM64_REG_W14,
ARM64_REG_W15, UC_ARM64_REG_W15,
ARM64_REG_W16, UC_ARM64_REG_W16,
ARM64_REG_W17, UC_ARM64_REG_W17,
ARM64_REG_W18, UC_ARM64_REG_W18,
ARM64_REG_W19, UC_ARM64_REG_W19,
ARM64_REG_W20, UC_ARM64_REG_W20,
ARM64_REG_W21, UC_ARM64_REG_W21,
ARM64_REG_W22, UC_ARM64_REG_W22,
ARM64_REG_W23, UC_ARM64_REG_W23,
ARM64_REG_W24, UC_ARM64_REG_W24,
ARM64_REG_W25, UC_ARM64_REG_W25,
ARM64_REG_W26, UC_ARM64_REG_W26,
ARM64_REG_W27, UC_ARM64_REG_W27,
ARM64_REG_W28, UC_ARM64_REG_W28,
ARM64_REG_W29, UC_ARM64_REG_W29,
ARM64_REG_W30, UC_ARM64_REG_W30,
ARM64_REG_X0, UC_ARM64_REG_X0,
ARM64_REG_X1, UC_ARM64_REG_X1,
ARM64_REG_X2, UC_ARM64_REG_X2,
ARM64_REG_X3, UC_ARM64_REG_X3,
ARM64_REG_X4, UC_ARM64_REG_X4,
ARM64_REG_X5, UC_ARM64_REG_X5,
ARM64_REG_X6, UC_ARM64_REG_X6,
ARM64_REG_X7, UC_ARM64_REG_X7,
ARM64_REG_X8, UC_ARM64_REG_X8,
ARM64_REG_X9, UC_ARM64_REG_X9,
ARM64_REG_X10, UC_ARM64_REG_X10,
ARM64_REG_X11, UC_ARM64_REG_X11,
ARM64_REG_X12, UC_ARM64_REG_X12,
ARM64_REG_X13, UC_ARM64_REG_X13,
ARM64_REG_X14, UC_ARM64_REG_X14,
ARM64_REG_X15, UC_ARM64_REG_X15,
ARM64_REG_X16, UC_ARM64_REG_X16,
ARM64_REG_X17, UC_ARM64_REG_X17,
ARM64_REG_X18, UC_ARM64_REG_X18,
ARM64_REG_X19, UC_ARM64_REG_X19,
ARM64_REG_X20, UC_ARM64_REG_X20,
ARM64_REG_X21, UC_ARM64_REG_X21,
ARM64_REG_X22, UC_ARM64_REG_X22,
ARM64_REG_X23, UC_ARM64_REG_X23,
ARM64_REG_X24, UC_ARM64_REG_X24,
ARM64_REG_X25, UC_ARM64_REG_X25,
ARM64_REG_X26, UC_ARM64_REG_X26,
ARM64_REG_X27, UC_ARM64_REG_X27,
ARM64_REG_X28, UC_ARM64_REG_X28,
ARM64_REG_V0, UC_ARM64_REG_V0,
ARM64_REG_V1, UC_ARM64_REG_V1,
ARM64_REG_V2, UC_ARM64_REG_V2,
ARM64_REG_V3, UC_ARM64_REG_V3,
ARM64_REG_V4, UC_ARM64_REG_V4,
ARM64_REG_V5, UC_ARM64_REG_V5,
ARM64_REG_V6, UC_ARM64_REG_V6,
ARM64_REG_V7, UC_ARM64_REG_V7,
ARM64_REG_V8, UC_ARM64_REG_V8,
ARM64_REG_V9, UC_ARM64_REG_V9,
ARM64_REG_V10, UC_ARM64_REG_V10,
ARM64_REG_V11, UC_ARM64_REG_V11,
ARM64_REG_V12, UC_ARM64_REG_V12,
ARM64_REG_V13, UC_ARM64_REG_V13,
ARM64_REG_V14, UC_ARM64_REG_V14,
ARM64_REG_V15, UC_ARM64_REG_V15,
ARM64_REG_V16, UC_ARM64_REG_V16,
ARM64_REG_V17, UC_ARM64_REG_V17,
ARM64_REG_V18, UC_ARM64_REG_V18,
ARM64_REG_V19, UC_ARM64_REG_V19,
ARM64_REG_V20, UC_ARM64_REG_V20,
ARM64_REG_V21, UC_ARM64_REG_V21,
ARM64_REG_V22, UC_ARM64_REG_V22,
ARM64_REG_V23, UC_ARM64_REG_V23,
ARM64_REG_V24, UC_ARM64_REG_V24,
ARM64_REG_V25, UC_ARM64_REG_V25,
ARM64_REG_V26, UC_ARM64_REG_V26,
ARM64_REG_V27, UC_ARM64_REG_V27,
ARM64_REG_V28, UC_ARM64_REG_V28,
ARM64_REG_V29, UC_ARM64_REG_V29,
ARM64_REG_V30, UC_ARM64_REG_V30,
ARM64_REG_V31, UC_ARM64_REG_V31,
//> pseudo registers //> pseudo registers
ARM64_REG_PC, // program counter register UC_ARM64_REG_PC, // program counter register
ARM64_REG_ENDING, // <-- mark the end of the list of registers UC_ARM64_REG_ENDING, // <-- mark the end of the list of registers
//> alias registers //> alias registers
ARM64_REG_IP1 = ARM64_REG_X16, UC_ARM64_REG_IP1 = UC_ARM64_REG_X16,
ARM64_REG_IP0 = ARM64_REG_X17, UC_ARM64_REG_IP0 = UC_ARM64_REG_X17,
ARM64_REG_FP = ARM64_REG_X29, UC_ARM64_REG_FP = UC_ARM64_REG_X29,
ARM64_REG_LR = ARM64_REG_X30, UC_ARM64_REG_LR = UC_ARM64_REG_X30,
} arm64_reg; } uc_arm64_reg;
#ifdef __cplusplus #ifdef __cplusplus
} }

40
include/unicorn/m68k.h
View file

@ -17,30 +17,30 @@ extern "C" {
//> M68K registers //> M68K registers
typedef enum m68k_reg { typedef enum m68k_reg {
M68K_REG_INVALID = 0, UC_M68K_REG_INVALID = 0,
M68K_REG_A0, UC_M68K_REG_A0,
M68K_REG_A1, UC_M68K_REG_A1,
M68K_REG_A2, UC_M68K_REG_A2,
M68K_REG_A3, UC_M68K_REG_A3,
M68K_REG_A4, UC_M68K_REG_A4,
M68K_REG_A5, UC_M68K_REG_A5,
M68K_REG_A6, UC_M68K_REG_A6,
M68K_REG_A7, UC_M68K_REG_A7,
M68K_REG_D0, UC_M68K_REG_D0,
M68K_REG_D1, UC_M68K_REG_D1,
M68K_REG_D2, UC_M68K_REG_D2,
M68K_REG_D3, UC_M68K_REG_D3,
M68K_REG_D4, UC_M68K_REG_D4,
M68K_REG_D5, UC_M68K_REG_D5,
M68K_REG_D6, UC_M68K_REG_D6,
M68K_REG_D7, UC_M68K_REG_D7,
M68K_REG_SR, UC_M68K_REG_SR,
M68K_REG_PC, UC_M68K_REG_PC,
M68K_REG_ENDING, // <-- mark the end of the list of registers UC_M68K_REG_ENDING, // <-- mark the end of the list of registers
} m68k_reg; } m68k_reg;
#ifdef __cplusplus #ifdef __cplusplus

360
include/unicorn/mips.h
View file

@ -17,207 +17,207 @@ extern "C" {
#endif #endif
//> MIPS registers //> MIPS registers
typedef enum mips_reg { typedef enum UC_MIPS_REG {
MIPS_REG_INVALID = 0, UC_MIPS_REG_INVALID = 0,
//> General purpose registers //> General purpose registers
MIPS_REG_PC, UC_MIPS_REG_PC,
MIPS_REG_0, UC_MIPS_REG_0,
MIPS_REG_1, UC_MIPS_REG_1,
MIPS_REG_2, UC_MIPS_REG_2,
MIPS_REG_3, UC_MIPS_REG_3,
MIPS_REG_4, UC_MIPS_REG_4,
MIPS_REG_5, UC_MIPS_REG_5,
MIPS_REG_6, UC_MIPS_REG_6,
MIPS_REG_7, UC_MIPS_REG_7,
MIPS_REG_8, UC_MIPS_REG_8,
MIPS_REG_9, UC_MIPS_REG_9,
MIPS_REG_10, UC_MIPS_REG_10,
MIPS_REG_11, UC_MIPS_REG_11,
MIPS_REG_12, UC_MIPS_REG_12,
MIPS_REG_13, UC_MIPS_REG_13,
MIPS_REG_14, UC_MIPS_REG_14,
MIPS_REG_15, UC_MIPS_REG_15,
MIPS_REG_16, UC_MIPS_REG_16,
MIPS_REG_17, UC_MIPS_REG_17,
MIPS_REG_18, UC_MIPS_REG_18,
MIPS_REG_19, UC_MIPS_REG_19,
MIPS_REG_20, UC_MIPS_REG_20,
MIPS_REG_21, UC_MIPS_REG_21,
MIPS_REG_22, UC_MIPS_REG_22,
MIPS_REG_23, UC_MIPS_REG_23,
MIPS_REG_24, UC_MIPS_REG_24,
MIPS_REG_25, UC_MIPS_REG_25,
MIPS_REG_26, UC_MIPS_REG_26,
MIPS_REG_27, UC_MIPS_REG_27,
MIPS_REG_28, UC_MIPS_REG_28,
MIPS_REG_29, UC_MIPS_REG_29,
MIPS_REG_30, UC_MIPS_REG_30,
MIPS_REG_31, UC_MIPS_REG_31,
//> DSP registers //> DSP registers
MIPS_REG_DSPCCOND, UC_MIPS_REG_DSPCCOND,
MIPS_REG_DSPCARRY, UC_MIPS_REG_DSPCARRY,
MIPS_REG_DSPEFI, UC_MIPS_REG_DSPEFI,
MIPS_REG_DSPOUTFLAG, UC_MIPS_REG_DSPOUTFLAG,
MIPS_REG_DSPOUTFLAG16_19, UC_MIPS_REG_DSPOUTFLAG16_19,
MIPS_REG_DSPOUTFLAG20, UC_MIPS_REG_DSPOUTFLAG20,
MIPS_REG_DSPOUTFLAG21, UC_MIPS_REG_DSPOUTFLAG21,
MIPS_REG_DSPOUTFLAG22, UC_MIPS_REG_DSPOUTFLAG22,
MIPS_REG_DSPOUTFLAG23, UC_MIPS_REG_DSPOUTFLAG23,
MIPS_REG_DSPPOS, UC_MIPS_REG_DSPPOS,
MIPS_REG_DSPSCOUNT, UC_MIPS_REG_DSPSCOUNT,
//> ACC registers //> ACC registers
MIPS_REG_AC0, UC_MIPS_REG_AC0,
MIPS_REG_AC1, UC_MIPS_REG_AC1,
MIPS_REG_AC2, UC_MIPS_REG_AC2,
MIPS_REG_AC3, UC_MIPS_REG_AC3,
//> COP registers //> COP registers
MIPS_REG_CC0, UC_MIPS_REG_CC0,
MIPS_REG_CC1, UC_MIPS_REG_CC1,
MIPS_REG_CC2, UC_MIPS_REG_CC2,
MIPS_REG_CC3, UC_MIPS_REG_CC3,
MIPS_REG_CC4, UC_MIPS_REG_CC4,
MIPS_REG_CC5, UC_MIPS_REG_CC5,
MIPS_REG_CC6, UC_MIPS_REG_CC6,
MIPS_REG_CC7, UC_MIPS_REG_CC7,
//> FPU registers //> FPU registers
MIPS_REG_F0, UC_MIPS_REG_F0,
MIPS_REG_F1, UC_MIPS_REG_F1,
MIPS_REG_F2, UC_MIPS_REG_F2,
MIPS_REG_F3, UC_MIPS_REG_F3,
MIPS_REG_F4, UC_MIPS_REG_F4,
MIPS_REG_F5, UC_MIPS_REG_F5,
MIPS_REG_F6, UC_MIPS_REG_F6,
MIPS_REG_F7, UC_MIPS_REG_F7,
MIPS_REG_F8, UC_MIPS_REG_F8,
MIPS_REG_F9, UC_MIPS_REG_F9,
MIPS_REG_F10, UC_MIPS_REG_F10,
MIPS_REG_F11, UC_MIPS_REG_F11,
MIPS_REG_F12, UC_MIPS_REG_F12,
MIPS_REG_F13, UC_MIPS_REG_F13,
MIPS_REG_F14, UC_MIPS_REG_F14,
MIPS_REG_F15, UC_MIPS_REG_F15,
MIPS_REG_F16, UC_MIPS_REG_F16,
MIPS_REG_F17, UC_MIPS_REG_F17,
MIPS_REG_F18, UC_MIPS_REG_F18,
MIPS_REG_F19, UC_MIPS_REG_F19,
MIPS_REG_F20, UC_MIPS_REG_F20,
MIPS_REG_F21, UC_MIPS_REG_F21,
MIPS_REG_F22, UC_MIPS_REG_F22,
MIPS_REG_F23, UC_MIPS_REG_F23,
MIPS_REG_F24, UC_MIPS_REG_F24,
MIPS_REG_F25, UC_MIPS_REG_F25,
MIPS_REG_F26, UC_MIPS_REG_F26,
MIPS_REG_F27, UC_MIPS_REG_F27,
MIPS_REG_F28, UC_MIPS_REG_F28,
MIPS_REG_F29, UC_MIPS_REG_F29,
MIPS_REG_F30, UC_MIPS_REG_F30,
MIPS_REG_F31, UC_MIPS_REG_F31,
MIPS_REG_FCC0, UC_MIPS_REG_FCC0,
MIPS_REG_FCC1, UC_MIPS_REG_FCC1,
MIPS_REG_FCC2, UC_MIPS_REG_FCC2,
MIPS_REG_FCC3, UC_MIPS_REG_FCC3,
MIPS_REG_FCC4, UC_MIPS_REG_FCC4,
MIPS_REG_FCC5, UC_MIPS_REG_FCC5,
MIPS_REG_FCC6, UC_MIPS_REG_FCC6,
MIPS_REG_FCC7, UC_MIPS_REG_FCC7,
//> AFPR128 //> AFPR128
MIPS_REG_W0, UC_MIPS_REG_W0,
MIPS_REG_W1, UC_MIPS_REG_W1,
MIPS_REG_W2, UC_MIPS_REG_W2,
MIPS_REG_W3, UC_MIPS_REG_W3,
MIPS_REG_W4, UC_MIPS_REG_W4,
MIPS_REG_W5, UC_MIPS_REG_W5,
MIPS_REG_W6, UC_MIPS_REG_W6,
MIPS_REG_W7, UC_MIPS_REG_W7,
MIPS_REG_W8, UC_MIPS_REG_W8,
MIPS_REG_W9, UC_MIPS_REG_W9,
MIPS_REG_W10, UC_MIPS_REG_W10,
MIPS_REG_W11, UC_MIPS_REG_W11,
MIPS_REG_W12, UC_MIPS_REG_W12,
MIPS_REG_W13, UC_MIPS_REG_W13,
MIPS_REG_W14, UC_MIPS_REG_W14,
MIPS_REG_W15, UC_MIPS_REG_W15,
MIPS_REG_W16, UC_MIPS_REG_W16,
MIPS_REG_W17, UC_MIPS_REG_W17,
MIPS_REG_W18, UC_MIPS_REG_W18,
MIPS_REG_W19, UC_MIPS_REG_W19,
MIPS_REG_W20, UC_MIPS_REG_W20,
MIPS_REG_W21, UC_MIPS_REG_W21,
MIPS_REG_W22, UC_MIPS_REG_W22,
MIPS_REG_W23, UC_MIPS_REG_W23,
MIPS_REG_W24, UC_MIPS_REG_W24,
MIPS_REG_W25, UC_MIPS_REG_W25,
MIPS_REG_W26, UC_MIPS_REG_W26,
MIPS_REG_W27, UC_MIPS_REG_W27,
MIPS_REG_W28, UC_MIPS_REG_W28,
MIPS_REG_W29, UC_MIPS_REG_W29,
MIPS_REG_W30, UC_MIPS_REG_W30,
MIPS_REG_W31, UC_MIPS_REG_W31,
MIPS_REG_HI, UC_MIPS_REG_HI,
MIPS_REG_LO, UC_MIPS_REG_LO,
MIPS_REG_P0, UC_MIPS_REG_P0,
MIPS_REG_P1, UC_MIPS_REG_P1,
MIPS_REG_P2, UC_MIPS_REG_P2,
MIPS_REG_MPL0, UC_MIPS_REG_MPL0,
MIPS_REG_MPL1, UC_MIPS_REG_MPL1,
MIPS_REG_MPL2, UC_MIPS_REG_MPL2,
MIPS_REG_ENDING, // <-- mark the end of the list or registers UC_MIPS_REG_ENDING, // <-- mark the end of the list or registers
// alias registers // alias registers
MIPS_REG_ZERO = MIPS_REG_0, UC_MIPS_REG_ZERO = UC_MIPS_REG_0,
MIPS_REG_AT = MIPS_REG_1, UC_MIPS_REG_AT = UC_MIPS_REG_1,
MIPS_REG_V0 = MIPS_REG_2, UC_MIPS_REG_V0 = UC_MIPS_REG_2,
MIPS_REG_V1 = MIPS_REG_3, UC_MIPS_REG_V1 = UC_MIPS_REG_3,
MIPS_REG_A0 = MIPS_REG_4, UC_MIPS_REG_A0 = UC_MIPS_REG_4,
MIPS_REG_A1 = MIPS_REG_5, UC_MIPS_REG_A1 = UC_MIPS_REG_5,
MIPS_REG_A2 = MIPS_REG_6, UC_MIPS_REG_A2 = UC_MIPS_REG_6,
MIPS_REG_A3 = MIPS_REG_7, UC_MIPS_REG_A3 = UC_MIPS_REG_7,
MIPS_REG_T0 = MIPS_REG_8, UC_MIPS_REG_T0 = UC_MIPS_REG_8,
MIPS_REG_T1 = MIPS_REG_9, UC_MIPS_REG_T1 = UC_MIPS_REG_9,
MIPS_REG_T2 = MIPS_REG_10, UC_MIPS_REG_T2 = UC_MIPS_REG_10,
MIPS_REG_T3 = MIPS_REG_11, UC_MIPS_REG_T3 = UC_MIPS_REG_11,
MIPS_REG_T4 = MIPS_REG_12, UC_MIPS_REG_T4 = UC_MIPS_REG_12,
MIPS_REG_T5 = MIPS_REG_13, UC_MIPS_REG_T5 = UC_MIPS_REG_13,
MIPS_REG_T6 = MIPS_REG_14, UC_MIPS_REG_T6 = UC_MIPS_REG_14,
MIPS_REG_T7 = MIPS_REG_15, UC_MIPS_REG_T7 = UC_MIPS_REG_15,
MIPS_REG_S0 = MIPS_REG_16, UC_MIPS_REG_S0 = UC_MIPS_REG_16,
MIPS_REG_S1 = MIPS_REG_17, UC_MIPS_REG_S1 = UC_MIPS_REG_17,
MIPS_REG_S2 = MIPS_REG_18, UC_MIPS_REG_S2 = UC_MIPS_REG_18,
MIPS_REG_S3 = MIPS_REG_19, UC_MIPS_REG_S3 = UC_MIPS_REG_19,
MIPS_REG_S4 = MIPS_REG_20, UC_MIPS_REG_S4 = UC_MIPS_REG_20,
MIPS_REG_S5 = MIPS_REG_21, UC_MIPS_REG_S5 = UC_MIPS_REG_21,
MIPS_REG_S6 = MIPS_REG_22, UC_MIPS_REG_S6 = UC_MIPS_REG_22,
MIPS_REG_S7 = MIPS_REG_23, UC_MIPS_REG_S7 = UC_MIPS_REG_23,
MIPS_REG_T8 = MIPS_REG_24, UC_MIPS_REG_T8 = UC_MIPS_REG_24,
MIPS_REG_T9 = MIPS_REG_25, UC_MIPS_REG_T9 = UC_MIPS_REG_25,
MIPS_REG_K0 = MIPS_REG_26, UC_MIPS_REG_K0 = UC_MIPS_REG_26,
MIPS_REG_K1 = MIPS_REG_27, UC_MIPS_REG_K1 = UC_MIPS_REG_27,
MIPS_REG_GP = MIPS_REG_28, UC_MIPS_REG_GP = UC_MIPS_REG_28,
MIPS_REG_SP = MIPS_REG_29, UC_MIPS_REG_SP = UC_MIPS_REG_29,
MIPS_REG_FP = MIPS_REG_30, MIPS_REG_S8 = MIPS_REG_30, UC_MIPS_REG_FP = UC_MIPS_REG_30, UC_MIPS_REG_S8 = UC_MIPS_REG_30,
MIPS_REG_RA = MIPS_REG_31, UC_MIPS_REG_RA = UC_MIPS_REG_31,
MIPS_REG_HI0 = MIPS_REG_AC0, UC_MIPS_REG_HI0 = UC_MIPS_REG_AC0,
MIPS_REG_HI1 = MIPS_REG_AC1, UC_MIPS_REG_HI1 = UC_MIPS_REG_AC1,
MIPS_REG_HI2 = MIPS_REG_AC2, UC_MIPS_REG_HI2 = UC_MIPS_REG_AC2,
MIPS_REG_HI3 = MIPS_REG_AC3, UC_MIPS_REG_HI3 = UC_MIPS_REG_AC3,
MIPS_REG_LO0 = MIPS_REG_HI0, UC_MIPS_REG_LO0 = UC_MIPS_REG_HI0,
MIPS_REG_LO1 = MIPS_REG_HI1, UC_MIPS_REG_LO1 = UC_MIPS_REG_HI1,
MIPS_REG_LO2 = MIPS_REG_HI2, UC_MIPS_REG_LO2 = UC_MIPS_REG_HI2,
MIPS_REG_LO3 = MIPS_REG_HI3, UC_MIPS_REG_LO3 = UC_MIPS_REG_HI3,
} mips_reg; } UC_MIPS_REG;
#ifdef __cplusplus #ifdef __cplusplus
} }

188
include/unicorn/sparc.h
View file

@ -20,108 +20,108 @@ extern "C" {
#endif #endif
//> SPARC registers //> SPARC registers
typedef enum sparc_reg { typedef enum uc_sparc_reg {
SPARC_REG_INVALID = 0, UC_SPARC_REG_INVALID = 0,
SPARC_REG_F0, UC_SPARC_REG_F0,
SPARC_REG_F1, UC_SPARC_REG_F1,
SPARC_REG_F2, UC_SPARC_REG_F2,
SPARC_REG_F3, UC_SPARC_REG_F3,
SPARC_REG_F4, UC_SPARC_REG_F4,
SPARC_REG_F5, UC_SPARC_REG_F5,
SPARC_REG_F6, UC_SPARC_REG_F6,
SPARC_REG_F7, UC_SPARC_REG_F7,
SPARC_REG_F8, UC_SPARC_REG_F8,
SPARC_REG_F9, UC_SPARC_REG_F9,
SPARC_REG_F10, UC_SPARC_REG_F10,
SPARC_REG_F11, UC_SPARC_REG_F11,
SPARC_REG_F12, UC_SPARC_REG_F12,
SPARC_REG_F13, UC_SPARC_REG_F13,
SPARC_REG_F14, UC_SPARC_REG_F14,
SPARC_REG_F15, UC_SPARC_REG_F15,
SPARC_REG_F16, UC_SPARC_REG_F16,
SPARC_REG_F17, UC_SPARC_REG_F17,
SPARC_REG_F18, UC_SPARC_REG_F18,
SPARC_REG_F19, UC_SPARC_REG_F19,
SPARC_REG_F20, UC_SPARC_REG_F20,
SPARC_REG_F21, UC_SPARC_REG_F21,
SPARC_REG_F22, UC_SPARC_REG_F22,
SPARC_REG_F23, UC_SPARC_REG_F23,
SPARC_REG_F24, UC_SPARC_REG_F24,
SPARC_REG_F25, UC_SPARC_REG_F25,
SPARC_REG_F26, UC_SPARC_REG_F26,
SPARC_REG_F27, UC_SPARC_REG_F27,
SPARC_REG_F28, UC_SPARC_REG_F28,
SPARC_REG_F29, UC_SPARC_REG_F29,
SPARC_REG_F30, UC_SPARC_REG_F30,
SPARC_REG_F31, UC_SPARC_REG_F31,
SPARC_REG_F32, UC_SPARC_REG_F32,
SPARC_REG_F34, UC_SPARC_REG_F34,
SPARC_REG_F36, UC_SPARC_REG_F36,
SPARC_REG_F38, UC_SPARC_REG_F38,
SPARC_REG_F40, UC_SPARC_REG_F40,
SPARC_REG_F42, UC_SPARC_REG_F42,
SPARC_REG_F44, UC_SPARC_REG_F44,
SPARC_REG_F46, UC_SPARC_REG_F46,
SPARC_REG_F48, UC_SPARC_REG_F48,
SPARC_REG_F50, UC_SPARC_REG_F50,
SPARC_REG_F52, UC_SPARC_REG_F52,
SPARC_REG_F54, UC_SPARC_REG_F54,
SPARC_REG_F56, UC_SPARC_REG_F56,
SPARC_REG_F58, UC_SPARC_REG_F58,
SPARC_REG_F60, UC_SPARC_REG_F60,
SPARC_REG_F62, UC_SPARC_REG_F62,
SPARC_REG_FCC0, // Floating condition codes UC_SPARC_REG_FCC0, // Floating condition codes
SPARC_REG_FCC1, UC_SPARC_REG_FCC1,
SPARC_REG_FCC2, UC_SPARC_REG_FCC2,
SPARC_REG_FCC3, UC_SPARC_REG_FCC3,
SPARC_REG_FP, UC_SPARC_REG_FP,
SPARC_REG_G0, UC_SPARC_REG_G0,
SPARC_REG_G1, UC_SPARC_REG_G1,
SPARC_REG_G2, UC_SPARC_REG_G2,
SPARC_REG_G3, UC_SPARC_REG_G3,
SPARC_REG_G4, UC_SPARC_REG_G4,
SPARC_REG_G5, UC_SPARC_REG_G5,
SPARC_REG_G6, UC_SPARC_REG_G6,
SPARC_REG_G7, UC_SPARC_REG_G7,
SPARC_REG_I0, UC_SPARC_REG_I0,
SPARC_REG_I1, UC_SPARC_REG_I1,
SPARC_REG_I2, UC_SPARC_REG_I2,
SPARC_REG_I3, UC_SPARC_REG_I3,
SPARC_REG_I4, UC_SPARC_REG_I4,
SPARC_REG_I5, UC_SPARC_REG_I5,
SPARC_REG_I7, UC_SPARC_REG_I7,
SPARC_REG_ICC, // Integer condition codes UC_SPARC_REG_ICC, // Integer condition codes
SPARC_REG_L0, UC_SPARC_REG_L0,
SPARC_REG_L1, UC_SPARC_REG_L1,
SPARC_REG_L2, UC_SPARC_REG_L2,
SPARC_REG_L3, UC_SPARC_REG_L3,
SPARC_REG_L4, UC_SPARC_REG_L4,
SPARC_REG_L5, UC_SPARC_REG_L5,
SPARC_REG_L6, UC_SPARC_REG_L6,
SPARC_REG_L7, UC_SPARC_REG_L7,
SPARC_REG_O0, UC_SPARC_REG_O0,
SPARC_REG_O1, UC_SPARC_REG_O1,
SPARC_REG_O2, UC_SPARC_REG_O2,
SPARC_REG_O3, UC_SPARC_REG_O3,
SPARC_REG_O4, UC_SPARC_REG_O4,
SPARC_REG_O5, UC_SPARC_REG_O5,
SPARC_REG_O7, UC_SPARC_REG_O7,
SPARC_REG_SP, UC_SPARC_REG_SP,
SPARC_REG_Y, UC_SPARC_REG_Y,
// special register // special register
SPARC_REG_XCC, UC_SPARC_REG_XCC,
// pseudo register // pseudo register
SPARC_REG_PC, // program counter register UC_SPARC_REG_PC, // program counter register
SPARC_REG_ENDING, // <-- mark the end of the list of registers UC_SPARC_REG_ENDING, // <-- mark the end of the list of registers
// extras // extras
SPARC_REG_O6 = SPARC_REG_SP, UC_SPARC_REG_O6 = UC_SPARC_REG_SP,
SPARC_REG_I6 = SPARC_REG_FP, UC_SPARC_REG_I6 = UC_SPARC_REG_FP,
} sparc_reg; } uc_sparc_reg;
#ifdef __cplusplus #ifdef __cplusplus
} }

17
include/unicorn/unicorn.h
View file

@ -19,6 +19,9 @@ extern "C" {
#include "platform.h" #include "platform.h"
// Handle to use with all APIs
typedef size_t uch;
#include "m68k.h" #include "m68k.h"
#include "x86.h" #include "x86.h"
#include "arm.h" #include "arm.h"
@ -65,9 +68,6 @@ extern "C" {
// 1 milisecond = 1000 nanoseconds // 1 milisecond = 1000 nanoseconds
#define UC_MILISECOND_SCALE 1000 #define UC_MILISECOND_SCALE 1000
// Handle using with all API
typedef size_t uch;
// Architecture type // Architecture type
typedef enum uc_arch { typedef enum uc_arch {
UC_ARCH_ARM = 1, // ARM architecture (including Thumb, Thumb-2) UC_ARCH_ARM = 1, // ARM architecture (including Thumb, Thumb-2)
@ -78,7 +78,6 @@ typedef enum uc_arch {
UC_ARCH_SPARC, // Sparc architecture UC_ARCH_SPARC, // Sparc architecture
UC_ARCH_M68K, // M68K architecture UC_ARCH_M68K, // M68K architecture
UC_ARCH_MAX, UC_ARCH_MAX,
UC_ARCH_ALL = 0xFFFF, // All architectures - for uc_support()
} uc_arch; } uc_arch;
// Mode type // Mode type
@ -116,6 +115,7 @@ typedef enum uc_err {
UC_ERR_CODE_INVALID, // Quit emulation due to invalid code address: uc_emu_start() UC_ERR_CODE_INVALID, // Quit emulation due to invalid code address: uc_emu_start()
UC_ERR_HOOK, // Invalid hook type: uc_hook_add() UC_ERR_HOOK, // Invalid hook type: uc_hook_add()
UC_ERR_INSN_INVALID, // Quit emulation due to invalid instruction: uc_emu_start() UC_ERR_INSN_INVALID, // Quit emulation due to invalid instruction: uc_emu_start()
UC_ERR_MAP, // Invalid memory mapping: uc_mem_map()
} uc_err; } uc_err;
@ -203,16 +203,14 @@ unsigned int uc_version(unsigned int *major, unsigned int *minor);
/* /*
This API can be used to either ask for archs supported by this library. Determine if the given architecture is supported by this library.
To check if a particular arch is supported by this library, set @query to @arch: architecture type (UC_ARCH_*)
arch mode (UC_ARCH_* value).
To verify if this library supports all the archs, use UC_ARCH_ALL.
@return True if this library supports the given arch. @return True if this library supports the given arch.
*/ */
UNICORN_EXPORT UNICORN_EXPORT
bool uc_support(int query); bool uc_arch_supported(uc_arch arch);
/* /*
@ -392,6 +390,7 @@ uc_err uc_hook_del(uch handle, uch *h2);
@handle: handle returned by uc_open() @handle: handle returned by uc_open()
@address: starting address of the new memory region to be mapped in. @address: starting address of the new memory region to be mapped in.
This address will be round down to 8KB boundary
@size: size of the new memory region to be mapped in. This will be round up to @size: size of the new memory region to be mapped in. This will be round up to
the next 8KB boundary. the next 8KB boundary.

2794
include/unicorn/x86.h
View file

File diff suppressed because it is too large Load diff

2
make.sh
View file

@ -54,7 +54,7 @@ install() {
PREFIX=/usr/local PREFIX=/usr/local
${MAKE} install ${MAKE} install
else # not OSX else # not OSX
test -d /usr/lib64 && ${MAKE} LIBDIRARCH=lib64 test -d /usr/lib64 && LIBDIRARCH=lib64
${MAKE} install ${MAKE} install
fi fi
} }

20
qemu/target-arm/unicorn_aarch64.c
View file

@ -43,18 +43,18 @@ int arm64_reg_read(uch handle, unsigned int regid, void *value)
mycpu = first_cpu; mycpu = first_cpu;
if (regid >= ARM64_REG_X0 && regid <= ARM64_REG_X28) if (regid >= UC_ARM64_REG_X0 && regid <= UC_ARM64_REG_X28)
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[regid - ARM64_REG_X0]; *(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_X0];
else { else {
switch(regid) { switch(regid) {
default: break; default: break;
case ARM64_REG_X29: case UC_ARM64_REG_X29:
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[29]; *(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[29];
break; break;
case ARM64_REG_X30: case UC_ARM64_REG_X30:
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[30]; *(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[30];
break; break;
case ARM64_REG_PC: case UC_ARM64_REG_PC:
*(uint64_t *)value = ARM_CPU(uc, mycpu)->env.pc; *(uint64_t *)value = ARM_CPU(uc, mycpu)->env.pc;
break; break;
} }
@ -75,18 +75,18 @@ int arm64_reg_write(uch handle, unsigned int regid, void *value)
mycpu = first_cpu; mycpu = first_cpu;
if (regid >= ARM64_REG_X0 && regid <= ARM64_REG_X28) if (regid >= UC_ARM64_REG_X0 && regid <= UC_ARM64_REG_X28)
ARM_CPU(uc, mycpu)->env.xregs[regid - ARM64_REG_X0] = *(int64_t *)value; ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_X0] = *(int64_t *)value;
else { else {
switch(regid) { switch(regid) {
default: break; default: break;
case ARM64_REG_X29: case UC_ARM64_REG_X29:
ARM_CPU(uc, mycpu)->env.xregs[29] = *(int64_t *)value; ARM_CPU(uc, mycpu)->env.xregs[29] = *(int64_t *)value;
break; break;
case ARM64_REG_X30: case UC_ARM64_REG_X30:
ARM_CPU(uc, mycpu)->env.xregs[30] = *(int64_t *)value; ARM_CPU(uc, mycpu)->env.xregs[30] = *(int64_t *)value;
break; break;
case ARM64_REG_PC: case UC_ARM64_REG_PC:
ARM_CPU(uc, mycpu)->env.pc = *(uint64_t *)value; ARM_CPU(uc, mycpu)->env.pc = *(uint64_t *)value;
break; break;
} }

32
qemu/target-arm/unicorn_arm.c
View file

@ -48,20 +48,20 @@ int arm_reg_read(uch handle, unsigned int regid, void *value)
break; break;
case UC_MODE_ARM: case UC_MODE_ARM:
case UC_MODE_THUMB: case UC_MODE_THUMB:
if (regid >= ARM_REG_R0 && regid <= ARM_REG_R12) if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12)
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[regid - ARM_REG_R0]; *(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[regid - UC_ARM_REG_R0];
else { else {
switch(regid) { switch(regid) {
//case ARM_REG_SP: //case UC_ARM_REG_SP:
case ARM_REG_R13: case UC_ARM_REG_R13:
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[13]; *(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[13];
break; break;
//case ARM_REG_LR: //case UC_ARM_REG_LR:
case ARM_REG_R14: case UC_ARM_REG_R14:
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[14]; *(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[14];
break; break;
//case ARM_REG_PC: //case UC_ARM_REG_PC:
case ARM_REG_R15: case UC_ARM_REG_R15:
*(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[15]; *(int32_t *)value = ARM_CPU(uc, mycpu)->env.regs[15];
break; break;
} }
@ -91,20 +91,20 @@ int arm_reg_write(uch handle, unsigned int regid, void *value)
case UC_MODE_ARM: case UC_MODE_ARM:
case UC_MODE_THUMB: case UC_MODE_THUMB:
if (regid >= ARM_REG_R0 && regid <= ARM_REG_R12) if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12)
ARM_CPU(uc, mycpu)->env.regs[regid - ARM_REG_R0] = *(int32_t *)value; ARM_CPU(uc, mycpu)->env.regs[regid - UC_ARM_REG_R0] = *(int32_t *)value;
else { else {
switch(regid) { switch(regid) {
//case ARM_REG_SP: //case UC_ARM_REG_SP:
case ARM_REG_R13: case UC_ARM_REG_R13:
ARM_CPU(uc, mycpu)->env.regs[13] = *(int32_t *)value; ARM_CPU(uc, mycpu)->env.regs[13] = *(int32_t *)value;
break; break;
//case ARM_REG_LR: //case UC_ARM_REG_LR:
case ARM_REG_R14: case UC_ARM_REG_R14:
ARM_CPU(uc, mycpu)->env.regs[14] = *(int32_t *)value; ARM_CPU(uc, mycpu)->env.regs[14] = *(int32_t *)value;
break; break;
//case ARM_REG_PC: //case UC_ARM_REG_PC:
case ARM_REG_R15: case UC_ARM_REG_R15:
ARM_CPU(uc, mycpu)->env.regs[15] = *(int32_t *)value; ARM_CPU(uc, mycpu)->env.regs[15] = *(int32_t *)value;
break; break;
} }

11
qemu/target-i386/seg_helper.c
View file

@ -22,6 +22,7 @@
#include "qemu/log.h" #include "qemu/log.h"
#include "exec/helper-proto.h" #include "exec/helper-proto.h"
#include "exec/cpu_ldst.h" #include "exec/cpu_ldst.h"
#include "uc_priv.h"
//#define DEBUG_PCALL //#define DEBUG_PCALL
@ -944,6 +945,16 @@ void helper_syscall(CPUX86State *env, int next_eip_addend)
#else #else
void helper_syscall(CPUX86State *env, int next_eip_addend) void helper_syscall(CPUX86State *env, int next_eip_addend)
{ {
// Unicorn: call interrupt callback if registered
struct uc_struct *uc = env->uc;
if (uc->hook_syscall_idx) {
((uc_cb_insn_syscall_t)uc->hook_callbacks[uc->hook_syscall_idx].callback)(
(uch)uc, uc->hook_callbacks[uc->hook_syscall_idx].user_data);
env->eip += next_eip_addend;
}
return;
int selector; int selector;
if (!(env->efer & MSR_EFER_SCE)) { if (!(env->efer & MSR_EFER_SCE)) {

500
qemu/target-i386/unicorn.c
View file

File diff suppressed because it is too large Load diff

20
qemu/target-m68k/unicorn.c
View file

@ -38,14 +38,14 @@ int m68k_reg_read(uch handle, unsigned int regid, void *value)
struct uc_struct *uc = (struct uc_struct *)handle; struct uc_struct *uc = (struct uc_struct *)handle;
CPUState *mycpu = first_cpu; CPUState *mycpu = first_cpu;
if (regid >= M68K_REG_A0 && regid <= M68K_REG_A7) if (regid >= UC_M68K_REG_A0 && regid <= UC_M68K_REG_A7)
*(int32_t *)value = M68K_CPU(uc, mycpu)->env.aregs[regid - M68K_REG_A0]; *(int32_t *)value = M68K_CPU(uc, mycpu)->env.aregs[regid - UC_M68K_REG_A0];
else if (regid >= M68K_REG_D0 && regid <= M68K_REG_D7) else if (regid >= UC_M68K_REG_D0 && regid <= UC_M68K_REG_D7)
*(int32_t *)value = M68K_CPU(uc, mycpu)->env.dregs[regid - M68K_REG_D0]; *(int32_t *)value = M68K_CPU(uc, mycpu)->env.dregs[regid - UC_M68K_REG_D0];
else { else {
switch(regid) { switch(regid) {
default: break; default: break;
case M68K_REG_PC: case UC_M68K_REG_PC:
*(int32_t *)value = M68K_CPU(uc, mycpu)->env.pc; *(int32_t *)value = M68K_CPU(uc, mycpu)->env.pc;
break; break;
} }
@ -65,14 +65,14 @@ int m68k_reg_write(uch handle, unsigned int regid, void *value)
struct uc_struct *uc = (struct uc_struct *) handle; struct uc_struct *uc = (struct uc_struct *) handle;
CPUState *mycpu = first_cpu; CPUState *mycpu = first_cpu;
if (regid >= M68K_REG_A0 && regid <= M68K_REG_A7) if (regid >= UC_M68K_REG_A0 && regid <= UC_M68K_REG_A7)
M68K_CPU(uc, mycpu)->env.aregs[regid - M68K_REG_A0] = *(int32_t *)value; M68K_CPU(uc, mycpu)->env.aregs[regid - UC_M68K_REG_A0] = *(int32_t *)value;
else if (regid >= M68K_REG_D0 && regid <= M68K_REG_D7) else if (regid >= UC_M68K_REG_D0 && regid <= UC_M68K_REG_D7)
M68K_CPU(uc, mycpu)->env.dregs[regid - M68K_REG_D0] = *(int32_t *)value; M68K_CPU(uc, mycpu)->env.dregs[regid - UC_M68K_REG_D0] = *(int32_t *)value;
else { else {
switch(regid) { switch(regid) {
default: break; default: break;
case M68K_REG_PC: case UC_M68K_REG_PC:
M68K_CPU(uc, mycpu)->env.pc = *(uint32_t *)value; M68K_CPU(uc, mycpu)->env.pc = *(uint32_t *)value;
break; break;
} }

12
qemu/target-mips/unicorn.c
View file

@ -37,12 +37,12 @@ int mips_reg_read(uch handle, unsigned int regid, void *value)
struct uc_struct *uc = (struct uc_struct *) handle; struct uc_struct *uc = (struct uc_struct *) handle;
CPUState *mycpu = first_cpu; CPUState *mycpu = first_cpu;
if (regid >= MIPS_REG_0 && regid <= MIPS_REG_31) if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31)
*(int32_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - MIPS_REG_0]; *(int32_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - UC_MIPS_REG_0];
else { else {
switch(regid) { switch(regid) {
default: break; default: break;
case MIPS_REG_PC: case UC_MIPS_REG_PC:
*(int32_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.PC; *(int32_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.PC;
break; break;
} }
@ -62,12 +62,12 @@ int mips_reg_write(uch handle, unsigned int regid, void *value)
struct uc_struct *uc = (struct uc_struct *) handle; struct uc_struct *uc = (struct uc_struct *) handle;
CPUState *mycpu = first_cpu; CPUState *mycpu = first_cpu;
if (regid >= MIPS_REG_0 && regid <= MIPS_REG_31) if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31)
MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - MIPS_REG_0] = *(int32_t *)value; MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - UC_MIPS_REG_0] = *(int32_t *)value;
else { else {
switch(regid) { switch(regid) {
default: break; default: break;
case MIPS_REG_PC: case UC_MIPS_REG_PC:
MIPS_CPU(uc, mycpu)->env.active_tc.PC = *(int32_t *)value; MIPS_CPU(uc, mycpu)->env.active_tc.PC = *(int32_t *)value;
break; break;
} }

12
qemu/target-sparc/unicorn.c
View file

@ -51,12 +51,12 @@ int sparc_reg_read(uch handle, unsigned int regid, void *value)
struct uc_struct *uc = (struct uc_struct *) handle; struct uc_struct *uc = (struct uc_struct *) handle;
CPUState *mycpu = first_cpu; CPUState *mycpu = first_cpu;
if (regid >= SPARC_REG_G0 && regid <= SPARC_REG_G7) if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)
*(int32_t *)value = SPARC_CPU(uc, mycpu)->env.gregs[regid - SPARC_REG_G0]; *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0];
else { else {
switch(regid) { switch(regid) {
default: break; default: break;
case SPARC_REG_PC: case UC_SPARC_REG_PC:
*(int32_t *)value = SPARC_CPU(uc, mycpu)->env.pc; *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.pc;
break; break;
} }
@ -76,12 +76,12 @@ int sparc_reg_write(uch handle, unsigned int regid, void *value)
struct uc_struct *uc = (struct uc_struct *) handle; struct uc_struct *uc = (struct uc_struct *) handle;
CPUState *mycpu = first_cpu; CPUState *mycpu = first_cpu;
if (regid >= SPARC_REG_G0 && regid <= SPARC_REG_G7) if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)
SPARC_CPU(uc, mycpu)->env.gregs[regid - SPARC_REG_G0] = *(int32_t *)value; SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(int32_t *)value;
else { else {
switch(regid) { switch(regid) {
default: break; default: break;
case SPARC_REG_PC: case UC_SPARC_REG_PC:
SPARC_CPU(uc, mycpu)->env.pc = *(uint32_t *)value; SPARC_CPU(uc, mycpu)->env.pc = *(uint32_t *)value;
SPARC_CPU(uc, mycpu)->env.npc = *(uint32_t *)value + 4; SPARC_CPU(uc, mycpu)->env.npc = *(uint32_t *)value + 4;
break; break;

12
qemu/target-sparc/unicorn64.c
View file

@ -34,12 +34,12 @@ int sparc_reg_read(uch handle, unsigned int regid, void *value)
struct uc_struct *uc = (struct uc_struct *) handle; struct uc_struct *uc = (struct uc_struct *) handle;
CPUState *mycpu = first_cpu; CPUState *mycpu = first_cpu;
if (regid >= SPARC_REG_G0 && regid <= SPARC_REG_G7) if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)
*(int32_t *)value = SPARC_CPU(uc, mycpu)->env.gregs[regid - SPARC_REG_G0]; *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0];
else { else {
switch(regid) { switch(regid) {
default: break; default: break;
case SPARC_REG_PC: case UC_SPARC_REG_PC:
*(int32_t *)value = SPARC_CPU(uc, mycpu)->env.pc; *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.pc;
break; break;
} }
@ -59,12 +59,12 @@ int sparc_reg_write(uch handle, unsigned int regid, void *value)
struct uc_struct *uc = (struct uc_struct *) handle; struct uc_struct *uc = (struct uc_struct *) handle;
CPUState *mycpu = first_cpu; CPUState *mycpu = first_cpu;
if (regid >= SPARC_REG_G0 && regid <= SPARC_REG_G7) if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)
SPARC_CPU(uc, mycpu)->env.gregs[regid - SPARC_REG_G0] = *(int32_t *)value; SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(int32_t *)value;
else { else {
switch(regid) { switch(regid) {
default: break; default: break;
case SPARC_REG_PC: case UC_SPARC_REG_PC:
SPARC_CPU(uc, mycpu)->env.pc = *(uint32_t *)value; SPARC_CPU(uc, mycpu)->env.pc = *(uint32_t *)value;
SPARC_CPU(uc, mycpu)->env.npc = *(uint32_t *)value + 4; SPARC_CPU(uc, mycpu)->env.npc = *(uint32_t *)value + 4;
break; break;

56
regress/callback-pc.py Executable file
View file

@ -0,0 +1,56 @@
#!/usr/bin/env python
# reg_write() can't modify PC from within trace callbacks
from __future__ import print_function
from unicorn import *
from unicorn.arm_const import *
BASE_ADDRESS = 0x10000000
# sub sp, #0xc
THUMB_CODE = "\x83\xb0" * 5
# callback for tracing instructions
def hook_code(uc, address, size, user_data):
print(">>> Tracing instruction at 0x%x, instruction size = %u" % (address, size))
mu = user_data
print(">>> Setting PC to 0xffffffff")
mu.reg_write(ARM_REG_PC, 0xffffffff)
# callback for tracing basic blocks
def hook_block(uc, address, size, user_data):
print(">>> Tracing basic block at 0x%x, block size = 0x%x" %(address, size))
mu = user_data
print(">>> Setting PC to 0xffffffff")
mu.reg_write(ARM_REG_PC, 0xffffffff)
# set up emulation
def instruction_trace_test():
try:
# initialize emulator in ARM's Thumb mode
mu = Uc(UC_ARCH_ARM, UC_MODE_THUMB)
# map some memory
mu.mem_map(BASE_ADDRESS, 2 * 1024 * 1024)
# write machine code to be emulated to memory
mu.mem_write(BASE_ADDRESS, THUMB_CODE)
# setup stack
mu.reg_write(UC_ARM_REG_SP, BASE_ADDRESS + 2 * 1024 * 1024)
# tracing all instructions with customized callback
mu.hook_add(UC_HOOK_CODE, hook_code, user_data=mu)
# tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block, user_data=mu)
# emulate machine code in infinite time
mu.emu_start(BASE_ADDRESS, BASE_ADDRESS + len(THUMB_CODE))
except UcError as e:
print("ERROR: %s" % e)
if __name__ == '__main__':
instruction_trace_test()

4
regress/crash_tb.py
View file

@ -20,7 +20,7 @@ mu.mem_write(CODE_ADDR, binary1)
# emu for maximum 1 sec. # emu for maximum 1 sec.
mu.emu_start(CODE_ADDR, len(binary1), UC_SECOND_SCALE) mu.emu_start(CODE_ADDR, len(binary1), UC_SECOND_SCALE)
print("RAX = %x" %mu.reg_read(X86_REG_RAX)) print("RAX = %x" %mu.reg_read(UC_X86_REG_RAX))
# write machine code to be emulated to memory # write machine code to be emulated to memory
mu.mem_write(CODE_ADDR, binary2) mu.mem_write(CODE_ADDR, binary2)
@ -28,5 +28,5 @@ mu.mem_write(CODE_ADDR, binary2)
# emu for maximum 1 sec. # emu for maximum 1 sec.
mu.emu_start(CODE_ADDR, len(binary2), UC_SECOND_SCALE) mu.emu_start(CODE_ADDR, len(binary2), UC_SECOND_SCALE)
print("RAX = %x" %mu.reg_read(X86_REG_RAX)) print("RAX = %x" %mu.reg_read(UC_X86_REG_RAX))

11
regress/deadlock_1.py Executable file
View file

@ -0,0 +1,11 @@
#!/usr/bin/python
# From issue #1 of Ryan Hileman
from unicorn import *
CODE = b"\x90\x91\x92"
mu = Uc(UC_ARCH_X86, UC_MODE_64)
mu.mem_map(0x100000, 4 * 1024)
mu.mem_write(0x100000, CODE)
mu.emu_start(0x100000, 0x1000 + len(CODE))

6
regress/hang.py
View file

@ -17,13 +17,13 @@ def hook_code(uc, address, size, user_data):
# callback for tracing Linux interrupt # callback for tracing Linux interrupt
def hook_intr(uc, intno, user_data): def hook_intr(uc, intno, user_data):
# only handle Linux syscall # only handle Linux syscall
rip = uc.reg_read(X86_REG_RIP) rip = uc.reg_read(UC_X86_REG_RIP)
if intno != 0x80: if intno != 0x80:
print("=== 0x%x: got interrupt %x, quit" %(rip, intno)); print("=== 0x%x: got interrupt %x, quit" %(rip, intno));
uc.emu_stop() uc.emu_stop()
return return
eax = uc.reg_read(X86_REG_EAX) eax = uc.reg_read(UC_X86_REG_EAX)
print(">>> 0x%x: interrupt 0x%x, EAX = 0x%x" %(rip, intno, eax)) print(">>> 0x%x: interrupt 0x%x, EAX = 0x%x" %(rip, intno, eax))
@ -40,7 +40,7 @@ mu.hook_add(UC_HOOK_CODE, hook_code)
mu.hook_add(UC_HOOK_INTR, hook_intr) mu.hook_add(UC_HOOK_INTR, hook_intr)
# setup stack # setup stack
mu.reg_write(X86_REG_RSP, 1024 * 1024) mu.reg_write(UC_X86_REG_RSP, 1024 * 1024)
# fill in memory with 0xCC (software breakpoint int 3) # fill in memory with 0xCC (software breakpoint int 3)
for i in xrange(1 * 1024): for i in xrange(1 * 1024):

14
regress/memmap.py Executable file
View file

@ -0,0 +1,14 @@
#!/usr/bin/python
# By Ryan Hileman, issue #9
# this prints out 2 lines and the contents must be the same
from unicorn import *
uc = Uc(UC_ARCH_X86, UC_MODE_64)
uc.mem_map(0x8048000, 0x2000)
uc.mem_write(0x8048000, 'test')
print 1, str(uc.mem_read(0x8048000, 4)).encode('hex')
uc.mem_map(0x804a000, 0x8000)
print 2, str(uc.mem_read(0x8048000, 4)).encode('hex')

8
regress/memmap_assert.py Executable file
View file

@ -0,0 +1,8 @@
#!/usr/bin/env python
import unicorn
u = unicorn.Uc(unicorn.UC_ARCH_X86, unicorn.UC_MODE_32)
u.mem_map(0x2000, 0)
u.mem_map(0x4000, 1)
print "I am never reached"

25
regress/memmap_segfault.py Executable file
View file

@ -0,0 +1,25 @@
#!/usr/bin/env python
import unicorn
u = unicorn.Uc(unicorn.UC_ARCH_X86, unicorn.UC_MODE_32)
u.mem_map(0x2000, 0x1000)
u.mem_read(0x2000, 1)
for i in range(20):
try:
u = unicorn.Uc(unicorn.UC_ARCH_X86, unicorn.UC_MODE_32)
u.mem_map(i*0x1000, 5)
u.mem_read(i*0x1000, 1)
print hex(i*0x1000) + " succeeeded"
except unicorn.UcError:
print hex(i*0x1000) + " failed"
for i in range(20):
try:
u = unicorn.Uc(unicorn.UC_ARCH_X86, unicorn.UC_MODE_32)
u.mem_map(i*0x1000, 5)
u.mem_read(i*0x1000, 1)
print hex(i*0x1000) + " succeeeded"
except unicorn.UcError:
print hex(i*0x1000) + " failed"

12
regress/memmap_weirdness.py Executable file
View file

@ -0,0 +1,12 @@
#!/usr/bin/env python
import unicorn
for i in range(20):
#try:
u = unicorn.Uc(unicorn.UC_ARCH_X86, unicorn.UC_MODE_32)
u.mem_map(i*0x1000, 5)
u.mem_read(i*0x1000+6, 1)
print hex(i*0x1000) + " succeeeded"
#except unicorn.UcError as e:
# print hex(i*0x1000) + " failed:",e

28
regress/movsd.py Executable file
View file

@ -0,0 +1,28 @@
#!/usr/bin/python
# By Ryan Hileman, issue #3
from capstone import *
from unicorn import *
from unicorn.x86_const import *
code = 'f20f1005aa120000'.decode('hex')
def dis(mem, addr):
md = Cs(CS_ARCH_X86, CS_MODE_64)
return '\n'.join([
'%s %s' % (i.mnemonic, i.op_str)
for i in md.disasm(str(mem), addr)
])
def hook_code(uc, addr, size, user_data):
mem = uc.mem_read(addr, size)
print 'instruction size:', size
print 'instruction:', str(mem).encode('hex'), dis(mem, addr)
print 'reference: ', code.encode('hex'), dis(code, addr)
addr = 0x400000
mu = Uc(UC_ARCH_X86, UC_MODE_64)
mu.hook_add(UC_HOOK_CODE, hook_code)
mu.mem_map(addr, 8 * 1024 * 1024)
mu.mem_write(addr, code)
mu.emu_start(addr, addr + len(code))

8
regress/wrong_rip.py
View file

@ -16,17 +16,17 @@ mu.mem_write(0, binary1 + binary2)
# emu for maximum 1 instruction. # emu for maximum 1 instruction.
mu.emu_start(0, 5, 0, 1) mu.emu_start(0, 5, 0, 1)
print("RAX = %u" %mu.reg_read(X86_REG_RAX)) print("RAX = %u" %mu.reg_read(UC_X86_REG_RAX))
pos = mu.reg_read(X86_REG_RIP) pos = mu.reg_read(UC_X86_REG_RIP)
print("RIP = %x" %pos) print("RIP = %x" %pos)
mu.emu_start(5, 10, 0, 1) mu.emu_start(5, 10, 0, 1)
pos = mu.reg_read(X86_REG_RIP) pos = mu.reg_read(UC_X86_REG_RIP)
print("RIP = %x" %pos) print("RIP = %x" %pos)
print("RAX = %u" %mu.reg_read(X86_REG_RAX)) print("RAX = %u" %mu.reg_read(UC_X86_REG_RAX))

8
regress/wrong_rip2.py
View file

@ -16,17 +16,17 @@ mu.mem_write(0, binary1 + binary2)
# emu for maximum 1 instruction. # emu for maximum 1 instruction.
mu.emu_start(0, 10, 0, 1) mu.emu_start(0, 10, 0, 1)
print("RAX = %u" %mu.reg_read(X86_REG_RAX)) print("RAX = %u" %mu.reg_read(UC_X86_REG_RAX))
pos = mu.reg_read(X86_REG_RIP) pos = mu.reg_read(UC_X86_REG_RIP)
print("RIP = %x" %pos) print("RIP = %x" %pos)
mu.emu_start(5, 10, 0, 1) mu.emu_start(5, 10, 0, 1)
pos = mu.reg_read(X86_REG_RIP) pos = mu.reg_read(UC_X86_REG_RIP)
print("RIP = %x" %pos) print("RIP = %x" %pos)
print("RAX = %u" %mu.reg_read(X86_REG_RAX)) print("RAX = %u" %mu.reg_read(UC_X86_REG_RAX))

4
regress/wrong_rip3.py
View file

@ -15,9 +15,9 @@ mu.mem_write(0, binary1)
# emu for maximum 1 instruction. # emu for maximum 1 instruction.
mu.emu_start(0, 10, 0, 1) mu.emu_start(0, 10, 0, 1)
print("EAX = %u" %mu.reg_read(X86_REG_EAX)) print("EAX = %u" %mu.reg_read(UC_X86_REG_EAX))
pos = mu.reg_read(X86_REG_EIP) pos = mu.reg_read(UC_X86_REG_EIP)
print("EIP = %x" %pos) print("EIP = %x" %pos)

8
regress/wrong_rip4.py
View file

@ -16,17 +16,17 @@ pos = 0
# emu for maximum 1 instruction. # emu for maximum 1 instruction.
mu.emu_start(pos, len(binary1), 0, 1) mu.emu_start(pos, len(binary1), 0, 1)
print("EAX = %u" %mu.reg_read(X86_REG_EAX)) print("EAX = %u" %mu.reg_read(UC_X86_REG_EAX))
pos = mu.reg_read(X86_REG_EIP) pos = mu.reg_read(UC_X86_REG_EIP)
print("EIP = %x" %pos) print("EIP = %x" %pos)
# emu to the end # emu to the end
mu.emu_start(pos, len(binary1)) mu.emu_start(pos, len(binary1))
print("EAX = %u" %mu.reg_read(X86_REG_EAX)) print("EAX = %u" %mu.reg_read(UC_X86_REG_EAX))
pos = mu.reg_read(X86_REG_EIP) pos = mu.reg_read(UC_X86_REG_EIP)
print("EIP = %x" %pos) print("EIP = %x" %pos)

22
regress/wrong_sp_arm.py Executable file
View file

@ -0,0 +1,22 @@
#!/usr/bin/python
# By Ryan Hileman, issue #16
from unicorn import *
from unicorn.arm_const import *
try:
uc = Uc(UC_ARCH_ARM, UC_MODE_32)
uc.reg_write(UC_ARM_REG_SP, 4)
print 'Writing 4 to SP'
print 'SP =', uc.reg_read(UC_ARM_REG_SP)
except UcError as e:
print("ERROR: %s" % e)
try:
print "==========="
uc = Uc(UC_ARCH_ARM, UC_MODE_ARM)
uc.reg_write(UC_ARM_REG_SP, 4)
print 'Writing 4 to SP'
print 'SP =', uc.reg_read(UC_ARM_REG_SP)
except UcError as e:
print("ERROR: %s" % e)

14
samples/sample_arm.c
View file

@ -53,9 +53,9 @@ static void test_arm(void)
uc_mem_write(handle, ADDRESS, (uint8_t *)ARM_CODE, sizeof(ARM_CODE) - 1); uc_mem_write(handle, ADDRESS, (uint8_t *)ARM_CODE, sizeof(ARM_CODE) - 1);
// initialize machine registers // initialize machine registers
uc_reg_write(handle, ARM_REG_R0, &r0); uc_reg_write(handle, UC_ARM_REG_R0, &r0);
uc_reg_write(handle, ARM_REG_R2, &r2); uc_reg_write(handle, UC_ARM_REG_R2, &r2);
uc_reg_write(handle, ARM_REG_R3, &r3); uc_reg_write(handle, UC_ARM_REG_R3, &r3);
// tracing all basic blocks with customized callback // tracing all basic blocks with customized callback
uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0); uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0);
@ -73,8 +73,8 @@ static void test_arm(void)
// now print out some registers // now print out some registers
printf(">>> Emulation done. Below is the CPU context\n"); printf(">>> Emulation done. Below is the CPU context\n");
uc_reg_read(handle, ARM_REG_R0, &r0); uc_reg_read(handle, UC_ARM_REG_R0, &r0);
uc_reg_read(handle, ARM_REG_R1, &r1); uc_reg_read(handle, UC_ARM_REG_R1, &r1);
printf(">>> R0 = 0x%x\n", r0); printf(">>> R0 = 0x%x\n", r0);
printf(">>> R1 = 0x%x\n", r1); printf(">>> R1 = 0x%x\n", r1);
@ -106,7 +106,7 @@ static void test_thumb(void)
uc_mem_write(handle, ADDRESS, (uint8_t *)THUMB_CODE, sizeof(THUMB_CODE) - 1); uc_mem_write(handle, ADDRESS, (uint8_t *)THUMB_CODE, sizeof(THUMB_CODE) - 1);
// initialize machine registers // initialize machine registers
uc_reg_write(handle, ARM_REG_SP, &sp); uc_reg_write(handle, UC_ARM_REG_SP, &sp);
// tracing all basic blocks with customized callback // tracing all basic blocks with customized callback
uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0); uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0);
@ -124,7 +124,7 @@ static void test_thumb(void)
// now print out some registers // now print out some registers
printf(">>> Emulation done. Below is the CPU context\n"); printf(">>> Emulation done. Below is the CPU context\n");
uc_reg_read(handle, ARM_REG_SP, &sp); uc_reg_read(handle, UC_ARM_REG_SP, &sp);
printf(">>> SP = 0x%x\n", sp); printf(">>> SP = 0x%x\n", sp);
uc_close(&handle); uc_close(&handle);

8
samples/sample_arm64.c
View file

@ -51,9 +51,9 @@ static void test_arm64(void)
uc_mem_write(handle, ADDRESS, (uint8_t *)ARM_CODE, sizeof(ARM_CODE) - 1); uc_mem_write(handle, ADDRESS, (uint8_t *)ARM_CODE, sizeof(ARM_CODE) - 1);
// initialize machine registers // initialize machine registers
uc_reg_write(handle, ARM64_REG_X11, &x11); uc_reg_write(handle, UC_ARM64_REG_X11, &x11);
uc_reg_write(handle, ARM64_REG_X13, &x13); uc_reg_write(handle, UC_ARM64_REG_X13, &x13);
uc_reg_write(handle, ARM64_REG_X15, &x15); uc_reg_write(handle, UC_ARM64_REG_X15, &x15);
// tracing all basic blocks with customized callback // tracing all basic blocks with customized callback
uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0); uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0);
@ -71,7 +71,7 @@ static void test_arm64(void)
// now print out some registers // now print out some registers
printf(">>> Emulation done. Below is the CPU context\n"); printf(">>> Emulation done. Below is the CPU context\n");
uc_reg_read(handle, ARM64_REG_X11, &x11); uc_reg_read(handle, UC_ARM64_REG_X11, &x11);
printf(">>> X11 = 0x%" PRIx64 "\n", x11); printf(">>> X11 = 0x%" PRIx64 "\n", x11);
uc_close(&handle); uc_close(&handle);

72
samples/sample_m68k.c
View file

@ -66,26 +66,26 @@ static void test_m68k(void)
uc_mem_write(handle, ADDRESS, (uint8_t *)M68K_CODE, sizeof(M68K_CODE) - 1); uc_mem_write(handle, ADDRESS, (uint8_t *)M68K_CODE, sizeof(M68K_CODE) - 1);
// initialize machine registers // initialize machine registers
uc_reg_write(handle, M68K_REG_D0, &d0); uc_reg_write(handle, UC_M68K_REG_D0, &d0);
uc_reg_write(handle, M68K_REG_D1, &d1); uc_reg_write(handle, UC_M68K_REG_D1, &d1);
uc_reg_write(handle, M68K_REG_D2, &d2); uc_reg_write(handle, UC_M68K_REG_D2, &d2);
uc_reg_write(handle, M68K_REG_D3, &d3); uc_reg_write(handle, UC_M68K_REG_D3, &d3);
uc_reg_write(handle, M68K_REG_D4, &d4); uc_reg_write(handle, UC_M68K_REG_D4, &d4);
uc_reg_write(handle, M68K_REG_D5, &d5); uc_reg_write(handle, UC_M68K_REG_D5, &d5);
uc_reg_write(handle, M68K_REG_D6, &d6); uc_reg_write(handle, UC_M68K_REG_D6, &d6);
uc_reg_write(handle, M68K_REG_D7, &d7); uc_reg_write(handle, UC_M68K_REG_D7, &d7);
uc_reg_write(handle, M68K_REG_A0, &a0); uc_reg_write(handle, UC_M68K_REG_A0, &a0);
uc_reg_write(handle, M68K_REG_A1, &a1); uc_reg_write(handle, UC_M68K_REG_A1, &a1);
uc_reg_write(handle, M68K_REG_A2, &a2); uc_reg_write(handle, UC_M68K_REG_A2, &a2);
uc_reg_write(handle, M68K_REG_A3, &a3); uc_reg_write(handle, UC_M68K_REG_A3, &a3);
uc_reg_write(handle, M68K_REG_A4, &a4); uc_reg_write(handle, UC_M68K_REG_A4, &a4);
uc_reg_write(handle, M68K_REG_A5, &a5); uc_reg_write(handle, UC_M68K_REG_A5, &a5);
uc_reg_write(handle, M68K_REG_A6, &a6); uc_reg_write(handle, UC_M68K_REG_A6, &a6);
uc_reg_write(handle, M68K_REG_A7, &a7); uc_reg_write(handle, UC_M68K_REG_A7, &a7);
uc_reg_write(handle, M68K_REG_PC, &pc); uc_reg_write(handle, UC_M68K_REG_PC, &pc);
uc_reg_write(handle, M68K_REG_SR, &sr); uc_reg_write(handle, UC_M68K_REG_SR, &sr);
// tracing all basic blocks with customized callback // tracing all basic blocks with customized callback
uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0); uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0);
@ -103,26 +103,26 @@ static void test_m68k(void)
// now print out some registers // now print out some registers
printf(">>> Emulation done. Below is the CPU context\n"); printf(">>> Emulation done. Below is the CPU context\n");
uc_reg_read(handle, M68K_REG_D0, &d0); uc_reg_read(handle, UC_M68K_REG_D0, &d0);
uc_reg_read(handle, M68K_REG_D1, &d1); uc_reg_read(handle, UC_M68K_REG_D1, &d1);
uc_reg_read(handle, M68K_REG_D2, &d2); uc_reg_read(handle, UC_M68K_REG_D2, &d2);
uc_reg_read(handle, M68K_REG_D3, &d3); uc_reg_read(handle, UC_M68K_REG_D3, &d3);
uc_reg_read(handle, M68K_REG_D4, &d4); uc_reg_read(handle, UC_M68K_REG_D4, &d4);
uc_reg_read(handle, M68K_REG_D5, &d5); uc_reg_read(handle, UC_M68K_REG_D5, &d5);
uc_reg_read(handle, M68K_REG_D6, &d6); uc_reg_read(handle, UC_M68K_REG_D6, &d6);
uc_reg_read(handle, M68K_REG_D7, &d7); uc_reg_read(handle, UC_M68K_REG_D7, &d7);
uc_reg_read(handle, M68K_REG_A0, &a0); uc_reg_read(handle, UC_M68K_REG_A0, &a0);
uc_reg_read(handle, M68K_REG_A1, &a1); uc_reg_read(handle, UC_M68K_REG_A1, &a1);
uc_reg_read(handle, M68K_REG_A2, &a2); uc_reg_read(handle, UC_M68K_REG_A2, &a2);
uc_reg_read(handle, M68K_REG_A3, &a3); uc_reg_read(handle, UC_M68K_REG_A3, &a3);
uc_reg_read(handle, M68K_REG_A4, &a4); uc_reg_read(handle, UC_M68K_REG_A4, &a4);
uc_reg_read(handle, M68K_REG_A5, &a5); uc_reg_read(handle, UC_M68K_REG_A5, &a5);
uc_reg_read(handle, M68K_REG_A6, &a6); uc_reg_read(handle, UC_M68K_REG_A6, &a6);
uc_reg_read(handle, M68K_REG_A7, &a7); uc_reg_read(handle, UC_M68K_REG_A7, &a7);
uc_reg_read(handle, M68K_REG_PC, &pc); uc_reg_read(handle, UC_M68K_REG_PC, &pc);
uc_reg_read(handle, M68K_REG_SR, &sr); uc_reg_read(handle, UC_M68K_REG_SR, &sr);
printf(">>> A0 = 0x%x\t\t>>> D0 = 0x%x\n", a0, d0); printf(">>> A0 = 0x%x\t\t>>> D0 = 0x%x\n", a0, d0);
printf(">>> A1 = 0x%x\t\t>>> D1 = 0x%x\n", a1, d1); printf(">>> A1 = 0x%x\t\t>>> D1 = 0x%x\n", a1, d1);

8
samples/sample_mips.c
View file

@ -50,7 +50,7 @@ static void test_mips_eb(void)
uc_mem_write(handle, ADDRESS, (uint8_t *)MIPS_CODE_EB, sizeof(MIPS_CODE_EB) - 1); uc_mem_write(handle, ADDRESS, (uint8_t *)MIPS_CODE_EB, sizeof(MIPS_CODE_EB) - 1);
// initialize machine registers // initialize machine registers
uc_reg_write(handle, MIPS_REG_1, &r1); uc_reg_write(handle, UC_MIPS_REG_1, &r1);
// tracing all basic blocks with customized callback // tracing all basic blocks with customized callback
uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0); uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0);
@ -68,7 +68,7 @@ static void test_mips_eb(void)
// now print out some registers // now print out some registers
printf(">>> Emulation done. Below is the CPU context\n"); printf(">>> Emulation done. Below is the CPU context\n");
uc_reg_read(handle, MIPS_REG_1, &r1); uc_reg_read(handle, UC_MIPS_REG_1, &r1);
printf(">>> R1 = 0x%x\n", r1); printf(">>> R1 = 0x%x\n", r1);
uc_close(&handle); uc_close(&handle);
@ -100,7 +100,7 @@ static void test_mips_el(void)
uc_mem_write(handle, ADDRESS, (uint8_t *)MIPS_CODE_EL, sizeof(MIPS_CODE_EL) - 1); uc_mem_write(handle, ADDRESS, (uint8_t *)MIPS_CODE_EL, sizeof(MIPS_CODE_EL) - 1);
// initialize machine registers // initialize machine registers
uc_reg_write(handle, MIPS_REG_1, &r1); uc_reg_write(handle, UC_MIPS_REG_1, &r1);
// tracing all basic blocks with customized callback // tracing all basic blocks with customized callback
uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0); uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0);
@ -118,7 +118,7 @@ static void test_mips_el(void)
// now print out some registers // now print out some registers
printf(">>> Emulation done. Below is the CPU context\n"); printf(">>> Emulation done. Below is the CPU context\n");
uc_reg_read(handle, MIPS_REG_1, &r1); uc_reg_read(handle, UC_MIPS_REG_1, &r1);
printf(">>> R1 = 0x%x\n", r1); printf(">>> R1 = 0x%x\n", r1);
uc_close(&handle); uc_close(&handle);

8
samples/sample_sparc.c
View file

@ -52,9 +52,9 @@ static void test_sparc(void)
uc_mem_write(handle, ADDRESS, (uint8_t *)SPARC_CODE, sizeof(SPARC_CODE) - 1); uc_mem_write(handle, ADDRESS, (uint8_t *)SPARC_CODE, sizeof(SPARC_CODE) - 1);
// initialize machine registers // initialize machine registers
uc_reg_write(handle, SPARC_REG_G1, &g1); uc_reg_write(handle, UC_SPARC_REG_G1, &g1);
uc_reg_write(handle, SPARC_REG_G2, &g2); uc_reg_write(handle, UC_SPARC_REG_G2, &g2);
uc_reg_write(handle, SPARC_REG_G3, &g3); uc_reg_write(handle, UC_SPARC_REG_G3, &g3);
// tracing all basic blocks with customized callback // tracing all basic blocks with customized callback
uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0); uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0);
@ -73,7 +73,7 @@ static void test_sparc(void)
// now print out some registers // now print out some registers
printf(">>> Emulation done. Below is the CPU context\n"); printf(">>> Emulation done. Below is the CPU context\n");
uc_reg_read(handle, SPARC_REG_G3, &g3); uc_reg_read(handle, UC_SPARC_REG_G3, &g3);
printf(">>> G3 = 0x%x\n", g3); printf(">>> G3 = 0x%x\n", g3);
uc_close(&handle); uc_close(&handle);

124
samples/sample_x86.c
View file

@ -41,7 +41,7 @@ static void hook_code(uch handle, uint64_t address, uint32_t size, void *user_da
int eflags; int eflags;
printf(">>> Tracing instruction at 0x%"PRIx64 ", instruction size = 0x%x\n", address, size); printf(">>> Tracing instruction at 0x%"PRIx64 ", instruction size = 0x%x\n", address, size);
uc_reg_read(handle, X86_REG_EFLAGS, &eflags); uc_reg_read(handle, UC_X86_REG_EFLAGS, &eflags);
printf(">>> --- EFLAGS is 0x%x\n", eflags); printf(">>> --- EFLAGS is 0x%x\n", eflags);
// Uncomment below code to stop the emulation using uc_emu_stop() // Uncomment below code to stop the emulation using uc_emu_stop()
@ -54,7 +54,7 @@ static void hook_code64(uch handle, uint64_t address, uint32_t size, void *user_
{ {
uint64_t rip; uint64_t rip;
uc_reg_read(handle, X86_REG_RIP, &rip); uc_reg_read(handle, UC_X86_REG_RIP, &rip);
printf(">>> Tracing instruction at 0x%"PRIx64 ", instruction size = 0x%x\n", address, size); printf(">>> Tracing instruction at 0x%"PRIx64 ", instruction size = 0x%x\n", address, size);
printf(">>> RIP is 0x%"PRIx64 "\n", rip); printf(">>> RIP is 0x%"PRIx64 "\n", rip);
@ -103,7 +103,7 @@ static uint32_t hook_in(uch handle, uint32_t port, int size, void *user_data)
{ {
uint32_t eip; uint32_t eip;
uc_reg_read(handle, X86_REG_EIP, &eip); uc_reg_read(handle, UC_X86_REG_EIP, &eip);
printf("--- reading from port 0x%x, size: %u, address: 0x%x\n", port, size, eip); printf("--- reading from port 0x%x, size: %u, address: 0x%x\n", port, size, eip);
@ -129,7 +129,7 @@ static void hook_out(uch handle, uint32_t port, int size, uint32_t value, void *
uint32_t tmp; uint32_t tmp;
uint32_t eip; uint32_t eip;
uc_reg_read(handle, X86_REG_EIP, &eip); uc_reg_read(handle, UC_X86_REG_EIP, &eip);
printf("--- writing to port 0x%x, size: %u, value: 0x%x, address: 0x%x\n", port, size, value, eip); printf("--- writing to port 0x%x, size: %u, value: 0x%x, address: 0x%x\n", port, size, value, eip);
@ -138,13 +138,13 @@ static void hook_out(uch handle, uint32_t port, int size, uint32_t value, void *
default: default:
return; // should never reach this return; // should never reach this
case 1: case 1:
uc_reg_read(handle, X86_REG_AL, &tmp); uc_reg_read(handle, UC_X86_REG_AL, &tmp);
break; break;
case 2: case 2:
uc_reg_read(handle, X86_REG_AX, &tmp); uc_reg_read(handle, UC_X86_REG_AX, &tmp);
break; break;
case 4: case 4:
uc_reg_read(handle, X86_REG_EAX, &tmp); uc_reg_read(handle, UC_X86_REG_EAX, &tmp);
break; break;
} }
@ -180,8 +180,8 @@ static void test_i386(void)
} }
// initialize machine registers // initialize machine registers
uc_reg_write(handle, X86_REG_ECX, &r_ecx); uc_reg_write(handle, UC_X86_REG_ECX, &r_ecx);
uc_reg_write(handle, X86_REG_EDX, &r_edx); uc_reg_write(handle, UC_X86_REG_EDX, &r_edx);
// tracing all basic blocks with customized callback // tracing all basic blocks with customized callback
uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0); uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0);
@ -199,8 +199,8 @@ static void test_i386(void)
// now print out some registers // now print out some registers
printf(">>> Emulation done. Below is the CPU context\n"); printf(">>> Emulation done. Below is the CPU context\n");
uc_reg_read(handle, X86_REG_ECX, &r_ecx); uc_reg_read(handle, UC_X86_REG_ECX, &r_ecx);
uc_reg_read(handle, X86_REG_EDX, &r_edx); uc_reg_read(handle, UC_X86_REG_EDX, &r_edx);
printf(">>> ECX = 0x%x\n", r_ecx); printf(">>> ECX = 0x%x\n", r_ecx);
printf(">>> EDX = 0x%x\n", r_edx); printf(">>> EDX = 0x%x\n", r_edx);
@ -286,8 +286,8 @@ static void test_i386_loop(void)
} }
// initialize machine registers // initialize machine registers
uc_reg_write(handle, X86_REG_ECX, &r_ecx); uc_reg_write(handle, UC_X86_REG_ECX, &r_ecx);
uc_reg_write(handle, X86_REG_EDX, &r_edx); uc_reg_write(handle, UC_X86_REG_EDX, &r_edx);
// emulate machine code in 2 seconds, so we can quit even // emulate machine code in 2 seconds, so we can quit even
// if the code loops // if the code loops
@ -300,8 +300,8 @@ static void test_i386_loop(void)
// now print out some registers // now print out some registers
printf(">>> Emulation done. Below is the CPU context\n"); printf(">>> Emulation done. Below is the CPU context\n");
uc_reg_read(handle, X86_REG_ECX, &r_ecx); uc_reg_read(handle, UC_X86_REG_ECX, &r_ecx);
uc_reg_read(handle, X86_REG_EDX, &r_edx); uc_reg_read(handle, UC_X86_REG_EDX, &r_edx);
printf(">>> ECX = 0x%x\n", r_ecx); printf(">>> ECX = 0x%x\n", r_ecx);
printf(">>> EDX = 0x%x\n", r_edx); printf(">>> EDX = 0x%x\n", r_edx);
@ -338,8 +338,8 @@ static void test_i386_invalid_mem_read(void)
} }
// initialize machine registers // initialize machine registers
uc_reg_write(handle, X86_REG_ECX, &r_ecx); uc_reg_write(handle, UC_X86_REG_ECX, &r_ecx);
uc_reg_write(handle, X86_REG_EDX, &r_edx); uc_reg_write(handle, UC_X86_REG_EDX, &r_edx);
// tracing all basic blocks with customized callback // tracing all basic blocks with customized callback
uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0); uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0);
@ -357,8 +357,8 @@ static void test_i386_invalid_mem_read(void)
// now print out some registers // now print out some registers
printf(">>> Emulation done. Below is the CPU context\n"); printf(">>> Emulation done. Below is the CPU context\n");
uc_reg_read(handle, X86_REG_ECX, &r_ecx); uc_reg_read(handle, UC_X86_REG_ECX, &r_ecx);
uc_reg_read(handle, X86_REG_EDX, &r_edx); uc_reg_read(handle, UC_X86_REG_EDX, &r_edx);
printf(">>> ECX = 0x%x\n", r_ecx); printf(">>> ECX = 0x%x\n", r_ecx);
printf(">>> EDX = 0x%x\n", r_edx); printf(">>> EDX = 0x%x\n", r_edx);
@ -396,8 +396,8 @@ static void test_i386_invalid_mem_write(void)
} }
// initialize machine registers // initialize machine registers
uc_reg_write(handle, X86_REG_ECX, &r_ecx); uc_reg_write(handle, UC_X86_REG_ECX, &r_ecx);
uc_reg_write(handle, X86_REG_EDX, &r_edx); uc_reg_write(handle, UC_X86_REG_EDX, &r_edx);
// tracing all basic blocks with customized callback // tracing all basic blocks with customized callback
uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0); uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0);
@ -418,8 +418,8 @@ static void test_i386_invalid_mem_write(void)
// now print out some registers // now print out some registers
printf(">>> Emulation done. Below is the CPU context\n"); printf(">>> Emulation done. Below is the CPU context\n");
uc_reg_read(handle, X86_REG_ECX, &r_ecx); uc_reg_read(handle, UC_X86_REG_ECX, &r_ecx);
uc_reg_read(handle, X86_REG_EDX, &r_edx); uc_reg_read(handle, UC_X86_REG_EDX, &r_edx);
printf(">>> ECX = 0x%x\n", r_ecx); printf(">>> ECX = 0x%x\n", r_ecx);
printf(">>> EDX = 0x%x\n", r_edx); printf(">>> EDX = 0x%x\n", r_edx);
@ -467,8 +467,8 @@ static void test_i386_jump_invalid(void)
} }
// initialize machine registers // initialize machine registers
uc_reg_write(handle, X86_REG_ECX, &r_ecx); uc_reg_write(handle, UC_X86_REG_ECX, &r_ecx);
uc_reg_write(handle, X86_REG_EDX, &r_edx); uc_reg_write(handle, UC_X86_REG_EDX, &r_edx);
// tracing all basic blocks with customized callback // tracing all basic blocks with customized callback
uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0); uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0);
@ -486,8 +486,8 @@ static void test_i386_jump_invalid(void)
// now print out some registers // now print out some registers
printf(">>> Emulation done. Below is the CPU context\n"); printf(">>> Emulation done. Below is the CPU context\n");
uc_reg_read(handle, X86_REG_ECX, &r_ecx); uc_reg_read(handle, UC_X86_REG_ECX, &r_ecx);
uc_reg_read(handle, X86_REG_EDX, &r_edx); uc_reg_read(handle, UC_X86_REG_EDX, &r_edx);
printf(">>> ECX = 0x%x\n", r_ecx); printf(">>> ECX = 0x%x\n", r_ecx);
printf(">>> EDX = 0x%x\n", r_edx); printf(">>> EDX = 0x%x\n", r_edx);
@ -524,8 +524,8 @@ static void test_i386_inout(void)
} }
// initialize machine registers // initialize machine registers
uc_reg_write(handle, X86_REG_EAX, &r_eax); uc_reg_write(handle, UC_X86_REG_EAX, &r_eax);
uc_reg_write(handle, X86_REG_ECX, &r_ecx); uc_reg_write(handle, UC_X86_REG_ECX, &r_ecx);
// tracing all basic blocks with customized callback // tracing all basic blocks with customized callback
uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0); uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0);
@ -534,9 +534,9 @@ static void test_i386_inout(void)
uc_hook_add(handle, &trace2, UC_HOOK_CODE, hook_code, NULL, (uint64_t)1, (uint64_t)0); uc_hook_add(handle, &trace2, UC_HOOK_CODE, hook_code, NULL, (uint64_t)1, (uint64_t)0);
// handle IN instruction // handle IN instruction
uc_hook_add(handle, &trace3, UC_HOOK_INSN, hook_in, NULL, X86_INS_IN); uc_hook_add(handle, &trace3, UC_HOOK_INSN, hook_in, NULL, UC_X86_INS_IN);
// handle OUT instruction // handle OUT instruction
uc_hook_add(handle, &trace4, UC_HOOK_INSN, hook_out, NULL, X86_INS_OUT); uc_hook_add(handle, &trace4, UC_HOOK_INSN, hook_out, NULL, UC_X86_INS_OUT);
// emulate machine code in infinite time // emulate machine code in infinite time
err = uc_emu_start(handle, ADDRESS, ADDRESS + sizeof(X86_CODE32_INOUT) - 1, 0, 0); err = uc_emu_start(handle, ADDRESS, ADDRESS + sizeof(X86_CODE32_INOUT) - 1, 0, 0);
@ -548,8 +548,8 @@ static void test_i386_inout(void)
// now print out some registers // now print out some registers
printf(">>> Emulation done. Below is the CPU context\n"); printf(">>> Emulation done. Below is the CPU context\n");
uc_reg_read(handle, X86_REG_EAX, &r_eax); uc_reg_read(handle, UC_X86_REG_EAX, &r_eax);
uc_reg_read(handle, X86_REG_ECX, &r_ecx); uc_reg_read(handle, UC_X86_REG_ECX, &r_ecx);
printf(">>> EAX = 0x%x\n", r_eax); printf(">>> EAX = 0x%x\n", r_eax);
printf(">>> ECX = 0x%x\n", r_ecx); printf(">>> ECX = 0x%x\n", r_ecx);
@ -599,22 +599,22 @@ static void test_x86_64(void)
} }
// initialize machine registers // initialize machine registers
uc_reg_write(handle, X86_REG_RSP, &rsp); uc_reg_write(handle, UC_X86_REG_RSP, &rsp);
uc_reg_write(handle, X86_REG_RAX, &rax); uc_reg_write(handle, UC_X86_REG_RAX, &rax);
uc_reg_write(handle, X86_REG_RBX, &rbx); uc_reg_write(handle, UC_X86_REG_RBX, &rbx);
uc_reg_write(handle, X86_REG_RCX, &rcx); uc_reg_write(handle, UC_X86_REG_RCX, &rcx);
uc_reg_write(handle, X86_REG_RDX, &rdx); uc_reg_write(handle, UC_X86_REG_RDX, &rdx);
uc_reg_write(handle, X86_REG_RSI, &rsi); uc_reg_write(handle, UC_X86_REG_RSI, &rsi);
uc_reg_write(handle, X86_REG_RDI, &rdi); uc_reg_write(handle, UC_X86_REG_RDI, &rdi);
uc_reg_write(handle, X86_REG_R8, &r8); uc_reg_write(handle, UC_X86_REG_R8, &r8);
uc_reg_write(handle, X86_REG_R9, &r9); uc_reg_write(handle, UC_X86_REG_R9, &r9);
uc_reg_write(handle, X86_REG_R10, &r10); uc_reg_write(handle, UC_X86_REG_R10, &r10);
uc_reg_write(handle, X86_REG_R11, &r11); uc_reg_write(handle, UC_X86_REG_R11, &r11);
uc_reg_write(handle, X86_REG_R12, &r12); uc_reg_write(handle, UC_X86_REG_R12, &r12);
uc_reg_write(handle, X86_REG_R13, &r13); uc_reg_write(handle, UC_X86_REG_R13, &r13);
uc_reg_write(handle, X86_REG_R14, &r14); uc_reg_write(handle, UC_X86_REG_R14, &r14);
uc_reg_write(handle, X86_REG_R15, &r15); uc_reg_write(handle, UC_X86_REG_R15, &r15);
// tracing all basic blocks with customized callback // tracing all basic blocks with customized callback
uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0); uc_hook_add(handle, &trace1, UC_HOOK_BLOCK, hook_block, NULL, (uint64_t)1, (uint64_t)0);
@ -639,20 +639,20 @@ static void test_x86_64(void)
// now print out some registers // now print out some registers
printf(">>> Emulation done. Below is the CPU context\n"); printf(">>> Emulation done. Below is the CPU context\n");
uc_reg_read(handle, X86_REG_RAX, &rax); uc_reg_read(handle, UC_X86_REG_RAX, &rax);
uc_reg_read(handle, X86_REG_RBX, &rbx); uc_reg_read(handle, UC_X86_REG_RBX, &rbx);
uc_reg_read(handle, X86_REG_RCX, &rcx); uc_reg_read(handle, UC_X86_REG_RCX, &rcx);
uc_reg_read(handle, X86_REG_RDX, &rdx); uc_reg_read(handle, UC_X86_REG_RDX, &rdx);
uc_reg_read(handle, X86_REG_RSI, &rsi); uc_reg_read(handle, UC_X86_REG_RSI, &rsi);
uc_reg_read(handle, X86_REG_RDI, &rdi); uc_reg_read(handle, UC_X86_REG_RDI, &rdi);
uc_reg_read(handle, X86_REG_R8, &r8); uc_reg_read(handle, UC_X86_REG_R8, &r8);
uc_reg_read(handle, X86_REG_R9, &r9); uc_reg_read(handle, UC_X86_REG_R9, &r9);
uc_reg_read(handle, X86_REG_R10, &r10); uc_reg_read(handle, UC_X86_REG_R10, &r10);
uc_reg_read(handle, X86_REG_R11, &r11); uc_reg_read(handle, UC_X86_REG_R11, &r11);
uc_reg_read(handle, X86_REG_R12, &r12); uc_reg_read(handle, UC_X86_REG_R12, &r12);
uc_reg_read(handle, X86_REG_R13, &r13); uc_reg_read(handle, UC_X86_REG_R13, &r13);
uc_reg_read(handle, X86_REG_R14, &r14); uc_reg_read(handle, UC_X86_REG_R14, &r14);
uc_reg_read(handle, X86_REG_R15, &r15); uc_reg_read(handle, UC_X86_REG_R15, &r15);
printf(">>> RAX = 0x%" PRIx64 "\n", rax); printf(">>> RAX = 0x%" PRIx64 "\n", rax);
printf(">>> RBX = 0x%" PRIx64 "\n", rbx); printf(">>> RBX = 0x%" PRIx64 "\n", rbx);

12
samples/shellcode.c
View file

@ -27,7 +27,7 @@ static void hook_code(uch handle, uint64_t address, uint32_t size, void *user_da
printf("Tracing instruction at 0x%"PRIx64 ", instruction size = 0x%x\n", address, size); printf("Tracing instruction at 0x%"PRIx64 ", instruction size = 0x%x\n", address, size);
uc_reg_read(handle, X86_REG_EIP, &r_eip); uc_reg_read(handle, UC_X86_REG_EIP, &r_eip);
printf("*** EIP = %x ***: ", r_eip); printf("*** EIP = %x ***: ", r_eip);
size = MIN(sizeof(tmp), size); size = MIN(sizeof(tmp), size);
@ -53,8 +53,8 @@ static void hook_intr(uch handle, uint32_t intno, void *user_data)
if (intno != 0x80) if (intno != 0x80)
return; return;
uc_reg_read(handle, X86_REG_EAX, &r_eax); uc_reg_read(handle, UC_X86_REG_EAX, &r_eax);
uc_reg_read(handle, X86_REG_EIP, &r_eip); uc_reg_read(handle, UC_X86_REG_EIP, &r_eip);
switch(r_eax) { switch(r_eax) {
default: default:
@ -66,10 +66,10 @@ static void hook_intr(uch handle, uint32_t intno, void *user_data)
break; break;
case 4: // sys_write case 4: // sys_write
// ECX = buffer address // ECX = buffer address
uc_reg_read(handle, X86_REG_ECX, &r_ecx); uc_reg_read(handle, UC_X86_REG_ECX, &r_ecx);
// EDX = buffer size // EDX = buffer size
uc_reg_read(handle, X86_REG_EDX, &r_edx); uc_reg_read(handle, UC_X86_REG_EDX, &r_edx);
// read the buffer in // read the buffer in
size = MIN(sizeof(buffer)-1, r_edx); size = MIN(sizeof(buffer)-1, r_edx);
@ -113,7 +113,7 @@ static void test_i386(void)
} }
// initialize machine registers // initialize machine registers
uc_reg_write(handle, X86_REG_ESP, &r_esp); uc_reg_write(handle, UC_X86_REG_ESP, &r_esp);
// tracing all instructions by having @begin > @end // tracing all instructions by having @begin > @end
uc_hook_add(handle, &trace1, UC_HOOK_CODE, hook_code, NULL, 1, 0); uc_hook_add(handle, &trace1, UC_HOOK_CODE, hook_code, NULL, 1, 0);

120
uc.c
View file

@ -36,43 +36,9 @@ static uint64_t map_begin[32], map_end[32];
static int map_count = 0; static int map_count = 0;
static unsigned int all_arch = 0;
static void archs_enable(void)
{
static bool initialized = false;
if (initialized)
return;
#ifdef UNICORN_HAS_ARM
all_arch = all_arch + (1 << UC_ARCH_ARM);
#endif
#ifdef UNICORN_HAS_ARM64
all_arch = all_arch + (1 << UC_ARCH_ARM64);
#endif
#ifdef UNICORN_HAS_MIPS
all_arch = all_arch + (1 << UC_ARCH_MIPS);
#endif
#ifdef UNICORN_HAS_SPARC
all_arch = all_arch + (1 << UC_ARCH_SPARC);
#endif
#ifdef UNICORN_HAS_M68K
all_arch = all_arch + (1 << UC_ARCH_M68K);
#endif
#ifdef UNICORN_HAS_X86
all_arch = all_arch + (1 << UC_ARCH_X86);
#endif
initialized = true;
}
UNICORN_EXPORT UNICORN_EXPORT
unsigned int uc_version(unsigned int *major, unsigned int *minor) unsigned int uc_version(unsigned int *major, unsigned int *minor)
{ {
archs_enable();
if (major != NULL && minor != NULL) { if (major != NULL && minor != NULL) {
*major = UC_API_MAJOR; *major = UC_API_MAJOR;
*minor = UC_API_MINOR; *minor = UC_API_MINOR;
@ -126,25 +92,41 @@ const char *uc_strerror(uc_err code)
return "Invalid instruction (UC_ERR_INSN_INVALID)"; return "Invalid instruction (UC_ERR_INSN_INVALID)";
case UC_ERR_HOOK: case UC_ERR_HOOK:
return "Invalid hook type (UC_ERR_HOOK)"; return "Invalid hook type (UC_ERR_HOOK)";
case UC_ERR_MAP:
return "Invalid memory mapping (UC_ERR_MAP)";
} }
} }
UNICORN_EXPORT UNICORN_EXPORT
bool uc_support(int query) bool uc_arch_supported(uc_arch arch)
{ {
archs_enable(); switch (arch) {
#ifdef UNICORN_HAS_ARM
case UC_ARCH_ARM: return true;
#endif
#ifdef UNICORN_HAS_ARM64
case UC_ARCH_ARM64: return true;
#endif
#ifdef UNICORN_HAS_M68K
case UC_ARCH_M68K: return true;
#endif
#ifdef UNICORN_HAS_MIPS
case UC_ARCH_MIPS: return true;
#endif
#ifdef UNICORN_HAS_PPC
case UC_ARCH_PPC: return true;
#endif
#ifdef UNICORN_HAS_SPARC
case UC_ARCH_SPARC: return true;
#endif
#ifdef UNICORN_HAS_X86
case UC_ARCH_X86: return true;
#endif
if (query == UC_ARCH_ALL) /* Invalid or disabled arch */
return all_arch == ((1 << UC_ARCH_ARM) | (1 << UC_ARCH_ARM64) | default: return false;
(1 << UC_ARCH_MIPS) | (1 << UC_ARCH_X86) | }
(1 << UC_ARCH_M68K) | (1 << UC_ARCH_SPARC));
if ((unsigned int)query < UC_ARCH_MAX)
return ((all_arch & (1 << query)) != 0);
// unsupported query
return false;
} }
@ -153,8 +135,6 @@ uc_err uc_open(uc_arch arch, uc_mode mode, uch *handle)
{ {
struct uc_struct *uc; struct uc_struct *uc;
archs_enable();
if (arch < UC_ARCH_MAX) { if (arch < UC_ARCH_MAX) {
uc = calloc(1, sizeof(*uc)); uc = calloc(1, sizeof(*uc));
if (!uc) { if (!uc) {
@ -197,6 +177,14 @@ uc_err uc_open(uc_arch arch, uc_mode mode, uch *handle)
#ifdef UNICORN_HAS_ARM #ifdef UNICORN_HAS_ARM
case UC_ARCH_ARM: case UC_ARCH_ARM:
uc->init_arch = arm_uc_init; uc->init_arch = arm_uc_init;
// verify mode
if (mode != UC_MODE_ARM && mode != UC_MODE_THUMB) {
*handle = 0;
free(uc);
return UC_ERR_MODE;
}
if (mode == UC_MODE_THUMB) if (mode == UC_MODE_THUMB)
uc->thumb = 1; uc->thumb = 1;
break; break;
@ -427,7 +415,7 @@ uc_err uc_emu_start(uch handle, uint64_t begin, uint64_t until, uint64_t timeout
break; break;
case UC_ARCH_M68K: case UC_ARCH_M68K:
uc_reg_write(handle, M68K_REG_PC, &begin); uc_reg_write(handle, UC_M68K_REG_PC, &begin);
break; break;
case UC_ARCH_X86: case UC_ARCH_X86:
@ -435,13 +423,13 @@ uc_err uc_emu_start(uch handle, uint64_t begin, uint64_t until, uint64_t timeout
default: default:
break; break;
case UC_MODE_16: case UC_MODE_16:
uc_reg_write(handle, X86_REG_IP, &begin); uc_reg_write(handle, UC_X86_REG_IP, &begin);
break; break;
case UC_MODE_32: case UC_MODE_32:
uc_reg_write(handle, X86_REG_EIP, &begin); uc_reg_write(handle, UC_X86_REG_EIP, &begin);
break; break;
case UC_MODE_64: case UC_MODE_64:
uc_reg_write(handle, X86_REG_RIP, &begin); uc_reg_write(handle, UC_X86_REG_RIP, &begin);
break; break;
} }
break; break;
@ -452,23 +440,23 @@ uc_err uc_emu_start(uch handle, uint64_t begin, uint64_t until, uint64_t timeout
break; break;
case UC_MODE_THUMB: case UC_MODE_THUMB:
case UC_MODE_ARM: case UC_MODE_ARM:
uc_reg_write(handle, ARM_REG_R15, &begin); uc_reg_write(handle, UC_ARM_REG_R15, &begin);
break; break;
} }
break; break;
case UC_ARCH_ARM64: case UC_ARCH_ARM64:
uc_reg_write(handle, ARM64_REG_PC, &begin); uc_reg_write(handle, UC_ARM64_REG_PC, &begin);
break; break;
case UC_ARCH_MIPS: case UC_ARCH_MIPS:
// TODO: MIPS32/MIPS64/BIGENDIAN etc // TODO: MIPS32/MIPS64/BIGENDIAN etc
uc_reg_write(handle, MIPS_REG_PC, &begin); uc_reg_write(handle, UC_MIPS_REG_PC, &begin);
break; break;
case UC_ARCH_SPARC: case UC_ARCH_SPARC:
// TODO: Sparc/Sparc64 // TODO: Sparc/Sparc64
uc_reg_write(handle, SPARC_REG_PC, &begin); uc_reg_write(handle, UC_SPARC_REG_PC, &begin);
break; break;
} }
@ -552,6 +540,10 @@ uc_err uc_mem_map(uch handle, uint64_t address, size_t size)
// invalid handle // invalid handle
return UC_ERR_UCH; return UC_ERR_UCH;
if (size == 0)
// invalid memory mapping
return UC_ERR_MAP;
// align to 8KB boundary // align to 8KB boundary
map_begin[map_count] = address & (~ (8*1024 - 1)); map_begin[map_count] = address & (~ (8*1024 - 1));
s = (size + 8*1024 - 1) & (~ (8*1024 - 1)); s = (size + 8*1024 - 1) & (~ (8*1024 - 1));
@ -623,7 +615,7 @@ static uc_err _hook_insn(struct uc_struct *uc, unsigned int insn_id, void *callb
case UC_ARCH_X86: case UC_ARCH_X86:
switch(insn_id) { switch(insn_id) {
default: break; default: break;
case X86_INS_OUT: case UC_X86_INS_OUT:
// FIXME: only one event handler at the same time // FIXME: only one event handler at the same time
i = hook_find_new(uc); i = hook_find_new(uc);
if (i) { if (i) {
@ -634,7 +626,7 @@ static uc_err _hook_insn(struct uc_struct *uc, unsigned int insn_id, void *callb
return UC_ERR_OK; return UC_ERR_OK;
} else } else
return UC_ERR_OOM; return UC_ERR_OOM;
case X86_INS_IN: case UC_X86_INS_IN:
// FIXME: only one event handler at the same time // FIXME: only one event handler at the same time
i = hook_find_new(uc); i = hook_find_new(uc);
if (i) { if (i) {
@ -645,6 +637,18 @@ static uc_err _hook_insn(struct uc_struct *uc, unsigned int insn_id, void *callb
return UC_ERR_OK; return UC_ERR_OK;
} else } else
return UC_ERR_OOM; return UC_ERR_OOM;
case UC_X86_INS_SYSCALL:
case UC_X86_INS_SYSENTER:
// FIXME: only one event handler at the same time
i = hook_find_new(uc);
if (i) {
uc->hook_callbacks[i].callback = callback;
uc->hook_callbacks[i].user_data = user_data;
*evh = i;
uc->hook_syscall_idx = i;
return UC_ERR_OK;
} else
return UC_ERR_OOM;
} }
break; break;
} }