fpu/softfloat: re-factor mul

We can now add float16_mul and use the common decompose and
canonicalize functions to have a single implementation for
float16/32/64 versions.

Backports commit 74d707e2cc1e406068acad8e5559cd2584b1073a from qemu

qemu/aarch64.h

@@ -492,6 +492,7 @@
 #define float16_is_quiet_nan float16_is_quiet_nan_aarch64
 #define float16_is_signaling_nan float16_is_signaling_nan_aarch64
 #define float16_maybe_silence_nan float16_maybe_silence_nan_aarch64
+#define float16_mul float16_mul_aarch64
 #define float16_squash_input_denormal float16_squash_input_denormal_aarch64
 #define float16_sub float16_sub_aarch64
 #define float16_to_float32 float16_to_float32_aarch64

qemu/aarch64eb.h

@@ -492,6 +492,7 @@
 #define float16_is_quiet_nan float16_is_quiet_nan_aarch64eb
 #define float16_is_signaling_nan float16_is_signaling_nan_aarch64eb
 #define float16_maybe_silence_nan float16_maybe_silence_nan_aarch64eb
+#define float16_mul float16_mul_aarch64eb
 #define float16_squash_input_denormal float16_squash_input_denormal_aarch64eb
 #define float16_sub float16_sub_aarch64eb
 #define float16_to_float32 float16_to_float32_aarch64eb

qemu/arm.h

@@ -492,6 +492,7 @@
 #define float16_is_quiet_nan float16_is_quiet_nan_arm
 #define float16_is_signaling_nan float16_is_signaling_nan_arm
 #define float16_maybe_silence_nan float16_maybe_silence_nan_arm
+#define float16_mul float16_mul_arm
 #define float16_squash_input_denormal float16_squash_input_denormal_arm
 #define float16_sub float16_sub_arm
 #define float16_to_float32 float16_to_float32_arm

qemu/armeb.h

@@ -492,6 +492,7 @@
 #define float16_is_quiet_nan float16_is_quiet_nan_armeb
 #define float16_is_signaling_nan float16_is_signaling_nan_armeb
 #define float16_maybe_silence_nan float16_maybe_silence_nan_armeb
+#define float16_mul float16_mul_armeb
 #define float16_squash_input_denormal float16_squash_input_denormal_armeb
 #define float16_sub float16_sub_armeb
 #define float16_to_float32 float16_to_float32_armeb

qemu/fpu/softfloat.c

@@ -735,6 +735,87 @@ float64 QEMU_FLATTEN float64_sub(float64 a, float64 b,
     return float64_round_pack_canonical(pr, status);
 }
 
+/*
+ * Returns the result of multiplying the floating-point values `a' and
+ * `b'. The operation is performed according to the IEC/IEEE Standard
+ * for Binary Floating-Point Arithmetic.
+ */
+
+static FloatParts mul_floats(FloatParts a, FloatParts b, float_status *s)
+{
+    bool sign = a.sign ^ b.sign;
+
+    if (a.cls == float_class_normal && b.cls == float_class_normal) {
+        uint64_t hi, lo;
+        int exp = a.exp + b.exp;
+
+        mul64To128(a.frac, b.frac, &hi, &lo);
+        shift128RightJamming(hi, lo, DECOMPOSED_BINARY_POINT, &hi, &lo);
+        if (lo & DECOMPOSED_OVERFLOW_BIT) {
+            shift64RightJamming(lo, 1, &lo);
+            exp += 1;
+        }
+
+        /* Re-use a */
+        a.exp = exp;
+        a.sign = sign;
+        a.frac = lo;
+        return a;
+    }
+    /* handle all the NaN cases */
+    if (is_nan(a.cls) || is_nan(b.cls)) {
+        return pick_nan(a, b, s);
+    }
+    /* Inf * Zero == NaN */
+    if ((a.cls == float_class_inf && b.cls == float_class_zero) ||
+        (a.cls == float_class_zero && b.cls == float_class_inf)) {
+        s->float_exception_flags |= float_flag_invalid;
+        a.cls = float_class_dnan;
+        a.sign = sign;
+        return a;
+    }
+    /* Multiply by 0 or Inf */
+    if (a.cls == float_class_inf || a.cls == float_class_zero) {
+        a.sign = sign;
+        return a;
+    }
+    if (b.cls == float_class_inf || b.cls == float_class_zero) {
+        b.sign = sign;
+        return b;
+    }
+    g_assert_not_reached();
+}
+
+float16 QEMU_FLATTEN float16_mul(float16 a, float16 b,
+                                 float_status *status)
+{
+    FloatParts pa = float16_unpack_canonical(a, status);
+    FloatParts pb = float16_unpack_canonical(b, status);
+    FloatParts pr = mul_floats(pa, pb, status);
+
+    return float16_round_pack_canonical(pr, status);
+}
+
+float32 QEMU_FLATTEN float32_mul(float32 a, float32 b,
+                                 float_status *status)
+{
+    FloatParts pa = float32_unpack_canonical(a, status);
+    FloatParts pb = float32_unpack_canonical(b, status);
+    FloatParts pr = mul_floats(pa, pb, status);
+
+    return float32_round_pack_canonical(pr, status);
+}
+
+float64 QEMU_FLATTEN float64_mul(float64 a, float64 b,
+                                 float_status *status)
+{
+    FloatParts pa = float64_unpack_canonical(a, status);
+    FloatParts pb = float64_unpack_canonical(b, status);
+    FloatParts pr = mul_floats(pa, pb, status);
+
+    return float64_round_pack_canonical(pr, status);
+}
+
 /*----------------------------------------------------------------------------
 | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6
 | and 7, and returns the properly rounded 32-bit integer corresponding to the
@@ -2515,72 +2596,6 @@ float32 float32_round_to_int(float32 a, float_status *status)
 
 }
 
-/*----------------------------------------------------------------------------
-| Returns the result of multiplying the single-precision floating-point values
-| `a' and `b'.  The operation is performed according to the IEC/IEEE Standard
-| for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float32 float32_mul(float32 a, float32 b, float_status *status)
-{
-    flag aSign, bSign, zSign;
-    int aExp, bExp, zExp;
-    uint32_t aSig, bSig;
-    uint64_t zSig64;
-    uint32_t zSig;
-
-    a = float32_squash_input_denormal(a, status);
-    b = float32_squash_input_denormal(b, status);
-
-    aSig = extractFloat32Frac( a );
-    aExp = extractFloat32Exp( a );
-    aSign = extractFloat32Sign( a );
-    bSig = extractFloat32Frac( b );
-    bExp = extractFloat32Exp( b );
-
-    bSign = extractFloat32Sign( b );
-    zSign = aSign ^ bSign;
-    if ( aExp == 0xFF ) {
-        if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) {
-            return propagateFloat32NaN(a, b, status);
-        }
-        if ( ( bExp | bSig ) == 0 ) {
-            float_raise(float_flag_invalid, status);
-            return float32_default_nan(status);
-        }
-        return packFloat32( zSign, 0xFF, 0 );
-    }
-    if ( bExp == 0xFF ) {
-        if (bSig) {
-            return propagateFloat32NaN(a, b, status);
-        }
-        if ( ( aExp | aSig ) == 0 ) {
-            float_raise(float_flag_invalid, status);
-            return float32_default_nan(status);
-        }
-        return packFloat32( zSign, 0xFF, 0 );
-    }
-    if ( aExp == 0 ) {
-        if ( aSig == 0 ) return packFloat32( zSign, 0, 0 );
-        normalizeFloat32Subnormal( aSig, &aExp, &aSig );
-    }
-    if ( bExp == 0 ) {
-        if ( bSig == 0 ) return packFloat32( zSign, 0, 0 );
-        normalizeFloat32Subnormal( bSig, &bExp, &bSig );
-    }
-    zExp = aExp + bExp - 0x7F;
-    aSig = ( aSig | 0x00800000 )<<7;
-    bSig = ( bSig | 0x00800000 )<<8;
-    shift64RightJamming( ( (uint64_t) aSig ) * bSig, 32, &zSig64 );
-    zSig = (uint32_t)zSig64;
-    if ( 0 <= (int32_t) ( zSig<<1 ) ) {
-        zSig <<= 1;
-        --zExp;
-    }
-    return roundAndPackFloat32( zSign, zExp, zSig, status );
-
-}
-
 /*----------------------------------------------------------------------------
 | Returns the result of dividing the single-precision floating-point value `a'
 | by the corresponding value `b'.  The operation is performed according to the
@@ -4109,69 +4124,6 @@ float64 float64_trunc_to_int(float64 a, float_status *status)
     return res;
 }
 
-/*----------------------------------------------------------------------------
-| Returns the result of multiplying the double-precision floating-point values
-| `a' and `b'.  The operation is performed according to the IEC/IEEE Standard
-| for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float64 float64_mul(float64 a, float64 b, float_status *status)
-{
-    flag aSign, bSign, zSign;
-    int aExp, bExp, zExp;
-    uint64_t aSig, bSig, zSig0, zSig1;
-
-    a = float64_squash_input_denormal(a, status);
-    b = float64_squash_input_denormal(b, status);
-
-    aSig = extractFloat64Frac( a );
-    aExp = extractFloat64Exp( a );
-    aSign = extractFloat64Sign( a );
-    bSig = extractFloat64Frac( b );
-    bExp = extractFloat64Exp( b );
-    bSign = extractFloat64Sign( b );
-    zSign = aSign ^ bSign;
-    if ( aExp == 0x7FF ) {
-        if ( aSig || ( ( bExp == 0x7FF ) && bSig ) ) {
-            return propagateFloat64NaN(a, b, status);
-        }
-        if ( ( bExp | bSig ) == 0 ) {
-            float_raise(float_flag_invalid, status);
-            return float64_default_nan(status);
-        }
-        return packFloat64( zSign, 0x7FF, 0 );
-    }
-    if ( bExp == 0x7FF ) {
-        if (bSig) {
-            return propagateFloat64NaN(a, b, status);
-        }
-        if ( ( aExp | aSig ) == 0 ) {
-            float_raise(float_flag_invalid, status);
-            return float64_default_nan(status);
-        }
-        return packFloat64( zSign, 0x7FF, 0 );
-    }
-    if ( aExp == 0 ) {
-        if ( aSig == 0 ) return packFloat64( zSign, 0, 0 );
-        normalizeFloat64Subnormal( aSig, &aExp, &aSig );
-    }
-    if ( bExp == 0 ) {
-        if ( bSig == 0 ) return packFloat64( zSign, 0, 0 );
-        normalizeFloat64Subnormal( bSig, &bExp, &bSig );
-    }
-    zExp = aExp + bExp - 0x3FF;
-    aSig = ( aSig | LIT64( 0x0010000000000000 ) )<<10;
-    bSig = ( bSig | LIT64( 0x0010000000000000 ) )<<11;
-    mul64To128( aSig, bSig, &zSig0, &zSig1 );
-    zSig0 |= ( zSig1 != 0 );
-    if ( 0 <= (int64_t) ( zSig0<<1 ) ) {
-        zSig0 <<= 1;
-        --zExp;
-    }
-    return roundAndPackFloat64( zSign, zExp, zSig0, status );
-
-}
-
 /*----------------------------------------------------------------------------
 | Returns the result of dividing the double-precision floating-point value `a'
 | by the corresponding value `b'.  The operation is performed according to

qemu/header_gen.py

@@ -498,6 +498,7 @@ symbols = (
     'float16_is_quiet_nan',
     'float16_is_signaling_nan',
     'float16_maybe_silence_nan',
+    'float16_mul',
     'float16_squash_input_denormal',
     'float16_sub',
     'float16_to_float32',

qemu/include/fpu/softfloat.h

@@ -246,6 +246,7 @@ float64 float16_to_float64(float16 a, flag ieee, float_status *status);
 
 float16 float16_add(float16, float16, float_status *status);
 float16 float16_sub(float16, float16, float_status *status);
+float16 float16_mul(float16, float16, float_status *status);
 
 int float16_is_quiet_nan(float16, float_status *status);
 int float16_is_signaling_nan(float16, float_status *status);

qemu/m68k.h

@@ -492,6 +492,7 @@
 #define float16_is_quiet_nan float16_is_quiet_nan_m68k
 #define float16_is_signaling_nan float16_is_signaling_nan_m68k
 #define float16_maybe_silence_nan float16_maybe_silence_nan_m68k
+#define float16_mul float16_mul_m68k
 #define float16_squash_input_denormal float16_squash_input_denormal_m68k
 #define float16_sub float16_sub_m68k
 #define float16_to_float32 float16_to_float32_m68k

qemu/mips.h

@@ -492,6 +492,7 @@
 #define float16_is_quiet_nan float16_is_quiet_nan_mips
 #define float16_is_signaling_nan float16_is_signaling_nan_mips
 #define float16_maybe_silence_nan float16_maybe_silence_nan_mips
+#define float16_mul float16_mul_mips
 #define float16_squash_input_denormal float16_squash_input_denormal_mips
 #define float16_sub float16_sub_mips
 #define float16_to_float32 float16_to_float32_mips

qemu/mips64.h

@@ -492,6 +492,7 @@
 #define float16_is_quiet_nan float16_is_quiet_nan_mips64
 #define float16_is_signaling_nan float16_is_signaling_nan_mips64
 #define float16_maybe_silence_nan float16_maybe_silence_nan_mips64
+#define float16_mul float16_mul_mips64
 #define float16_squash_input_denormal float16_squash_input_denormal_mips64
 #define float16_sub float16_sub_mips64
 #define float16_to_float32 float16_to_float32_mips64

qemu/mips64el.h

@@ -492,6 +492,7 @@
 #define float16_is_quiet_nan float16_is_quiet_nan_mips64el
 #define float16_is_signaling_nan float16_is_signaling_nan_mips64el
 #define float16_maybe_silence_nan float16_maybe_silence_nan_mips64el
+#define float16_mul float16_mul_mips64el
 #define float16_squash_input_denormal float16_squash_input_denormal_mips64el
 #define float16_sub float16_sub_mips64el
 #define float16_to_float32 float16_to_float32_mips64el

qemu/mipsel.h

@@ -492,6 +492,7 @@
 #define float16_is_quiet_nan float16_is_quiet_nan_mipsel
 #define float16_is_signaling_nan float16_is_signaling_nan_mipsel
 #define float16_maybe_silence_nan float16_maybe_silence_nan_mipsel
+#define float16_mul float16_mul_mipsel
 #define float16_squash_input_denormal float16_squash_input_denormal_mipsel
 #define float16_sub float16_sub_mipsel
 #define float16_to_float32 float16_to_float32_mipsel

qemu/powerpc.h

@@ -492,6 +492,7 @@
 #define float16_is_quiet_nan float16_is_quiet_nan_powerpc
 #define float16_is_signaling_nan float16_is_signaling_nan_powerpc
 #define float16_maybe_silence_nan float16_maybe_silence_nan_powerpc
+#define float16_mul float16_mul_powerpc
 #define float16_squash_input_denormal float16_squash_input_denormal_powerpc
 #define float16_sub float16_sub_powerpc
 #define float16_to_float32 float16_to_float32_powerpc

qemu/sparc.h

@@ -492,6 +492,7 @@
 #define float16_is_quiet_nan float16_is_quiet_nan_sparc
 #define float16_is_signaling_nan float16_is_signaling_nan_sparc
 #define float16_maybe_silence_nan float16_maybe_silence_nan_sparc
+#define float16_mul float16_mul_sparc
 #define float16_squash_input_denormal float16_squash_input_denormal_sparc
 #define float16_sub float16_sub_sparc
 #define float16_to_float32 float16_to_float32_sparc

qemu/sparc64.h

@@ -492,6 +492,7 @@
 #define float16_is_quiet_nan float16_is_quiet_nan_sparc64
 #define float16_is_signaling_nan float16_is_signaling_nan_sparc64
 #define float16_maybe_silence_nan float16_maybe_silence_nan_sparc64
+#define float16_mul float16_mul_sparc64
 #define float16_squash_input_denormal float16_squash_input_denormal_sparc64
 #define float16_sub float16_sub_sparc64
 #define float16_to_float32 float16_to_float32_sparc64

qemu/x86_64.h

@@ -492,6 +492,7 @@
 #define float16_is_quiet_nan float16_is_quiet_nan_x86_64
 #define float16_is_signaling_nan float16_is_signaling_nan_x86_64
 #define float16_maybe_silence_nan float16_maybe_silence_nan_x86_64
+#define float16_mul float16_mul_x86_64
 #define float16_squash_input_denormal float16_squash_input_denormal_x86_64
 #define float16_sub float16_sub_x86_64
 #define float16_to_float32 float16_to_float32_x86_64