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target/arm: Conditionalize DBGDIDR

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Only define the register if it exists for the cpu.

Backports 54a78718be6dd5fc6b6201f84bef8de5ac3b3802
This commit is contained in:
Richard Henderson 2021-03-04 15:42:01 -05:00 committed by Lioncash
parent 073923709f
commit 2c8f7b1fbc
1 changed files with 15 additions and 6 deletions
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21
qemu/target/arm/helper.c
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@ -6228,11 +6228,21 @@ static void define_debug_regs(ARMCPU *cpu)
*/ */
int i; int i;
int wrps, brps, ctx_cmps; int wrps, brps, ctx_cmps;
ARMCPRegInfo dbgdidr = {
.name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, /*
.access = PL0_R, .accessfn = access_tda, * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot
.type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr, * use AArch32. Given that bit 15 is RES1, if the value is 0 then
}; * the register must not exist for this cpu.
*/
if (cpu->isar.dbgdidr != 0) {
ARMCPRegInfo dbgdidr = {
.name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0,
.opc1 = 0, .opc2 = 0,
.access = PL0_R, .accessfn = access_tda,
.type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
};
define_one_arm_cp_reg(cpu, &dbgdidr);
}
/* Note that all these register fields hold "number of Xs minus 1". */ /* Note that all these register fields hold "number of Xs minus 1". */
brps = arm_num_brps(cpu); brps = arm_num_brps(cpu);
@ -6241,7 +6251,6 @@ static void define_debug_regs(ARMCPU *cpu)
assert(ctx_cmps <= brps); assert(ctx_cmps <= brps);
define_one_arm_cp_reg(cpu, &dbgdidr);
define_arm_cp_regs(cpu, debug_cp_reginfo); define_arm_cp_regs(cpu, debug_cp_reginfo);
if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {