target/arm: Implement SVE Floating Point Accumulating Reduction Group

Backports commit 7f9ddf64d5fe5bfaa91ae0ec52217d86f4d86452 from qemu
This commit is contained in:
Richard Henderson 2018-07-03 02:21:39 -04:00 committed by Lioncash
parent 44d89b4cb1
commit 2caa99929e
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
7 changed files with 123 additions and 0 deletions

View file

@ -3504,6 +3504,9 @@
#define helper_sve_fadd_d helper_sve_fadd_d_aarch64
#define helper_sve_fadd_h helper_sve_fadd_h_aarch64
#define helper_sve_fadd_s helper_sve_fadd_s_aarch64
#define helper_sve_fadda_d helper_sve_fadda_d_aarch64
#define helper_sve_fadda_h helper_sve_fadda_h_aarch64
#define helper_sve_fadda_s helper_sve_fadda_s_aarch64
#define helper_sve_fdiv_d helper_sve_fdiv_d_aarch64
#define helper_sve_fdiv_h helper_sve_fdiv_h_aarch64
#define helper_sve_fdiv_s helper_sve_fdiv_s_aarch64

View file

@ -3504,6 +3504,9 @@
#define helper_sve_fadd_d helper_sve_fadd_d_aarch64eb
#define helper_sve_fadd_h helper_sve_fadd_h_aarch64eb
#define helper_sve_fadd_s helper_sve_fadd_s_aarch64eb
#define helper_sve_fadda_d helper_sve_fadda_d_aarch64eb
#define helper_sve_fadda_h helper_sve_fadda_h_aarch64eb
#define helper_sve_fadda_s helper_sve_fadda_s_aarch64eb
#define helper_sve_fdiv_d helper_sve_fdiv_d_aarch64eb
#define helper_sve_fdiv_h helper_sve_fdiv_h_aarch64eb
#define helper_sve_fdiv_s helper_sve_fdiv_s_aarch64eb

View file

@ -3525,6 +3525,9 @@ aarch64_symbols = (
'helper_sve_fadd_d',
'helper_sve_fadd_h',
'helper_sve_fadd_s',
'helper_sve_fadda_d',
'helper_sve_fadda_h',
'helper_sve_fadda_s',
'helper_sve_fdiv_d',
'helper_sve_fdiv_h',
'helper_sve_fdiv_s',

View file

@ -720,6 +720,13 @@ DEF_HELPER_FLAGS_5(gvec_rsqrts_s, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_5(gvec_rsqrts_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fadda_h, TCG_CALL_NO_RWG,
i64, i64, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fadda_s, TCG_CALL_NO_RWG,
i64, i64, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_fadda_d, TCG_CALL_NO_RWG,
i64, i64, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(sve_fadd_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(sve_fadd_s, TCG_CALL_NO_RWG,

View file

@ -676,6 +676,11 @@ UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u
# SVE integer multiply immediate (unpredicated)
MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s
### SVE FP Accumulating Reduction Group
# SVE floating-point serial reduction (predicated)
FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm
### SVE Floating Point Arithmetic - Unpredicated Group
# SVE floating-point arithmetic (unpredicated)

View file

@ -3489,6 +3489,62 @@ void HELPER(sve_st4dd_r)(CPUARMState *env, void *vg,
}
}
uint64_t HELPER(sve_fadda_h)(uint64_t nn, void *vm, void *vg,
void *status, uint32_t desc)
{
intptr_t i = 0, opr_sz = simd_oprsz(desc);
float16 result = nn;
do {
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
do {
if (pg & 1) {
float16 mm = *(float16 *)(vm + H1_2(i));
result = float16_add(result, mm, status);
}
i += sizeof(float16), pg >>= sizeof(float16);
} while (i & 15);
} while (i < opr_sz);
return result;
}
uint64_t HELPER(sve_fadda_s)(uint64_t nn, void *vm, void *vg,
void *status, uint32_t desc)
{
intptr_t i = 0, opr_sz = simd_oprsz(desc);
float32 result = nn;
do {
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
do {
if (pg & 1) {
float32 mm = *(float32 *)(vm + H1_2(i));
result = float32_add(result, mm, status);
}
i += sizeof(float32), pg >>= sizeof(float32);
} while (i & 15);
} while (i < opr_sz);
return result;
}
uint64_t HELPER(sve_fadda_d)(uint64_t nn, void *vm, void *vg,
void *status, uint32_t desc)
{
intptr_t i = 0, opr_sz = simd_oprsz(desc) / 8;
uint64_t *m = vm;
uint8_t *pg = vg;
for (i = 0; i < opr_sz; i++) {
if (pg[H1(i)] & 1) {
nn = float64_add(nn, m[i], status);
}
}
return nn;
}
/* Fully general three-operand expander, controlled by a predicate,
* With the extra float_status parameter.
*/

View file

@ -3524,6 +3524,52 @@ DO_ZZI(UMIN, umin)
#undef DO_ZZI
/*
*** SVE Floating Point Accumulating Reduction Group
*/
static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
{
typedef void fadda_fn(TCGContext *, TCGv_i64, TCGv_i64, TCGv_ptr,
TCGv_ptr, TCGv_ptr, TCGv_i32);
static fadda_fn * const fns[3] = {
gen_helper_sve_fadda_h,
gen_helper_sve_fadda_s,
gen_helper_sve_fadda_d,
};
TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned vsz = vec_full_reg_size(s);
TCGv_ptr t_rm, t_pg, t_fpst;
TCGv_i64 t_val;
TCGv_i32 t_desc;
if (a->esz == 0) {
return false;
}
if (!sve_access_check(s)) {
return true;
}
t_val = load_esz(s, tcg_ctx->cpu_env, vec_reg_offset(s, a->rn, 0, a->esz), a->esz);
t_rm = tcg_temp_new_ptr(tcg_ctx);
t_pg = tcg_temp_new_ptr(tcg_ctx);
tcg_gen_addi_ptr(tcg_ctx, t_rm, tcg_ctx->cpu_env, vec_full_reg_offset(s, a->rm));
tcg_gen_addi_ptr(tcg_ctx, t_pg, tcg_ctx->cpu_env, pred_full_reg_offset(s, a->pg));
t_fpst = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16);
t_desc = tcg_const_i32(tcg_ctx, simd_desc(vsz, vsz, 0));
fns[a->esz - 1](tcg_ctx, t_val, t_val, t_rm, t_pg, t_fpst, t_desc);
tcg_temp_free_i32(tcg_ctx, t_desc);
tcg_temp_free_ptr(tcg_ctx, t_fpst);
tcg_temp_free_ptr(tcg_ctx, t_pg);
tcg_temp_free_ptr(tcg_ctx, t_rm);
write_fp_dreg(s, a->rd, t_val);
tcg_temp_free_i64(tcg_ctx, t_val);
return true;
}
/*
*** SVE Floating Point Arithmetic - Unpredicated Group
*/