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target/arm: Implement SVE Floating Point Accumulating Reduction Group
Backports commit 7f9ddf64d5fe5bfaa91ae0ec52217d86f4d86452 from qemu
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@ -3504,6 +3504,9 @@
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#define helper_sve_fadd_d helper_sve_fadd_d_aarch64
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#define helper_sve_fadd_h helper_sve_fadd_h_aarch64
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#define helper_sve_fadd_s helper_sve_fadd_s_aarch64
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#define helper_sve_fadda_d helper_sve_fadda_d_aarch64
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#define helper_sve_fadda_h helper_sve_fadda_h_aarch64
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#define helper_sve_fadda_s helper_sve_fadda_s_aarch64
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#define helper_sve_fdiv_d helper_sve_fdiv_d_aarch64
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#define helper_sve_fdiv_h helper_sve_fdiv_h_aarch64
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#define helper_sve_fdiv_s helper_sve_fdiv_s_aarch64
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@ -3504,6 +3504,9 @@
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#define helper_sve_fadd_d helper_sve_fadd_d_aarch64eb
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#define helper_sve_fadd_h helper_sve_fadd_h_aarch64eb
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#define helper_sve_fadd_s helper_sve_fadd_s_aarch64eb
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#define helper_sve_fadda_d helper_sve_fadda_d_aarch64eb
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#define helper_sve_fadda_h helper_sve_fadda_h_aarch64eb
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#define helper_sve_fadda_s helper_sve_fadda_s_aarch64eb
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#define helper_sve_fdiv_d helper_sve_fdiv_d_aarch64eb
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#define helper_sve_fdiv_h helper_sve_fdiv_h_aarch64eb
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#define helper_sve_fdiv_s helper_sve_fdiv_s_aarch64eb
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@ -3525,6 +3525,9 @@ aarch64_symbols = (
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'helper_sve_fadd_d',
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'helper_sve_fadd_h',
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'helper_sve_fadd_s',
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'helper_sve_fadda_d',
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'helper_sve_fadda_h',
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'helper_sve_fadda_s',
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'helper_sve_fdiv_d',
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'helper_sve_fdiv_h',
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'helper_sve_fdiv_s',
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@ -720,6 +720,13 @@ DEF_HELPER_FLAGS_5(gvec_rsqrts_s, TCG_CALL_NO_RWG,
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DEF_HELPER_FLAGS_5(gvec_rsqrts_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_fadda_h, TCG_CALL_NO_RWG,
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i64, i64, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_fadda_s, TCG_CALL_NO_RWG,
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i64, i64, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_fadda_d, TCG_CALL_NO_RWG,
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i64, i64, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fadd_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fadd_s, TCG_CALL_NO_RWG,
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@ -676,6 +676,11 @@ UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u
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# SVE integer multiply immediate (unpredicated)
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MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s
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### SVE FP Accumulating Reduction Group
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# SVE floating-point serial reduction (predicated)
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FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm
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### SVE Floating Point Arithmetic - Unpredicated Group
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# SVE floating-point arithmetic (unpredicated)
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@ -3489,6 +3489,62 @@ void HELPER(sve_st4dd_r)(CPUARMState *env, void *vg,
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}
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}
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uint64_t HELPER(sve_fadda_h)(uint64_t nn, void *vm, void *vg,
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void *status, uint32_t desc)
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{
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intptr_t i = 0, opr_sz = simd_oprsz(desc);
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float16 result = nn;
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do {
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uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
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do {
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if (pg & 1) {
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float16 mm = *(float16 *)(vm + H1_2(i));
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result = float16_add(result, mm, status);
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}
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i += sizeof(float16), pg >>= sizeof(float16);
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} while (i & 15);
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} while (i < opr_sz);
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return result;
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}
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uint64_t HELPER(sve_fadda_s)(uint64_t nn, void *vm, void *vg,
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void *status, uint32_t desc)
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{
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intptr_t i = 0, opr_sz = simd_oprsz(desc);
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float32 result = nn;
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do {
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uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
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do {
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if (pg & 1) {
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float32 mm = *(float32 *)(vm + H1_2(i));
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result = float32_add(result, mm, status);
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}
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i += sizeof(float32), pg >>= sizeof(float32);
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} while (i & 15);
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} while (i < opr_sz);
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return result;
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}
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uint64_t HELPER(sve_fadda_d)(uint64_t nn, void *vm, void *vg,
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void *status, uint32_t desc)
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{
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intptr_t i = 0, opr_sz = simd_oprsz(desc) / 8;
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uint64_t *m = vm;
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uint8_t *pg = vg;
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for (i = 0; i < opr_sz; i++) {
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if (pg[H1(i)] & 1) {
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nn = float64_add(nn, m[i], status);
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}
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}
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return nn;
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}
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/* Fully general three-operand expander, controlled by a predicate,
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* With the extra float_status parameter.
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*/
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@ -3524,6 +3524,52 @@ DO_ZZI(UMIN, umin)
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#undef DO_ZZI
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/*
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*** SVE Floating Point Accumulating Reduction Group
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*/
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static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
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{
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typedef void fadda_fn(TCGContext *, TCGv_i64, TCGv_i64, TCGv_ptr,
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TCGv_ptr, TCGv_ptr, TCGv_i32);
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static fadda_fn * const fns[3] = {
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gen_helper_sve_fadda_h,
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gen_helper_sve_fadda_s,
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gen_helper_sve_fadda_d,
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};
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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unsigned vsz = vec_full_reg_size(s);
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TCGv_ptr t_rm, t_pg, t_fpst;
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TCGv_i64 t_val;
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TCGv_i32 t_desc;
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if (a->esz == 0) {
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return false;
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}
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if (!sve_access_check(s)) {
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return true;
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}
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t_val = load_esz(s, tcg_ctx->cpu_env, vec_reg_offset(s, a->rn, 0, a->esz), a->esz);
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t_rm = tcg_temp_new_ptr(tcg_ctx);
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t_pg = tcg_temp_new_ptr(tcg_ctx);
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tcg_gen_addi_ptr(tcg_ctx, t_rm, tcg_ctx->cpu_env, vec_full_reg_offset(s, a->rm));
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tcg_gen_addi_ptr(tcg_ctx, t_pg, tcg_ctx->cpu_env, pred_full_reg_offset(s, a->pg));
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t_fpst = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16);
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t_desc = tcg_const_i32(tcg_ctx, simd_desc(vsz, vsz, 0));
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fns[a->esz - 1](tcg_ctx, t_val, t_val, t_rm, t_pg, t_fpst, t_desc);
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tcg_temp_free_i32(tcg_ctx, t_desc);
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tcg_temp_free_ptr(tcg_ctx, t_fpst);
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tcg_temp_free_ptr(tcg_ctx, t_pg);
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tcg_temp_free_ptr(tcg_ctx, t_rm);
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write_fp_dreg(s, a->rd, t_val);
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tcg_temp_free_i64(tcg_ctx, t_val);
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return true;
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}
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/*
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*** SVE Floating Point Arithmetic - Unpredicated Group
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*/
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