mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-03-23 03:45:14 +00:00
target/mips: Add a comment before each CP0 register section in cpu.h
Add a comment before each CP0 register section in CPUMIPSState definition, thus visually separating these sections. Backports commit 50e7edc5ac25af2faaacd1f91e177c7de7d696c3 from qemu
This commit is contained in:
Aleksandar Markovic
Lioncash
parent
d9ae47e2da
commit
2cf0f05c27
|
|
@ -304,11 +304,17 @@ struct CPUMIPSState {
|
|||
* 6 DataLo DataHi KScratch<n>
|
||||
* 7 TagLo TagHi KScratch<n>
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* CP0 Register 0
|
||||
*/
|
||||
int32_t CP0_Index;
|
||||
/* CP0_MVP* are per MVP registers. */
|
||||
int32_t CP0_VPControl;
|
||||
#define CP0VPCtl_DIS 0
|
||||
/*
|
||||
* CP0 Register 1
|
||||
*/
|
||||
int32_t CP0_Random;
|
||||
int32_t CP0_VPEControl;
|
||||
#define CP0VPECo_YSI 21
|
||||
|
|
@ -349,7 +355,13 @@ struct CPUMIPSState {
|
|||
#define CP0VPEOpt_DWX2 2
|
||||
#define CP0VPEOpt_DWX1 1
|
||||
#define CP0VPEOpt_DWX0 0
|
||||
/*
|
||||
* CP0 Register 2
|
||||
*/
|
||||
uint64_t CP0_EntryLo0;
|
||||
/*
|
||||
* CP0 Register 3
|
||||
*/
|
||||
uint64_t CP0_EntryLo1;
|
||||
#if defined(TARGET_MIPS64)
|
||||
# define CP0EnLo_RI 63
|
||||
|
|
@ -360,8 +372,14 @@ struct CPUMIPSState {
|
|||
#endif
|
||||
int32_t CP0_GlobalNumber;
|
||||
#define CP0GN_VPId 0
|
||||
/*
|
||||
* CP0 Register 4
|
||||
*/
|
||||
target_ulong CP0_Context;
|
||||
target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
|
||||
/*
|
||||
* CP0 Register 5
|
||||
*/
|
||||
int32_t CP0_PageMask;
|
||||
int32_t CP0_PageGrain_rw_bitmask;
|
||||
int32_t CP0_PageGrain;
|
||||
|
|
@ -399,6 +417,9 @@ struct CPUMIPSState {
|
|||
#define CP0SC2_XR 56
|
||||
#define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR)
|
||||
#define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)
|
||||
/*
|
||||
* CP0 Register 6
|
||||
*/
|
||||
int32_t CP0_Wired;
|
||||
int32_t CP0_SRSConf0_rw_bitmask;
|
||||
int32_t CP0_SRSConf0;
|
||||
|
|
@ -429,16 +450,34 @@ struct CPUMIPSState {
|
|||
#define CP0SRSC4_SRS15 20
|
||||
#define CP0SRSC4_SRS14 10
|
||||
#define CP0SRSC4_SRS13 0
|
||||
/*
|
||||
* CP0 Register 7
|
||||
*/
|
||||
int32_t CP0_HWREna;
|
||||
/*
|
||||
* CP0 Register 8
|
||||
*/
|
||||
target_ulong CP0_BadVAddr;
|
||||
uint32_t CP0_BadInstr;
|
||||
uint32_t CP0_BadInstrP;
|
||||
uint32_t CP0_BadInstrX;
|
||||
/*
|
||||
* CP0 Register 9
|
||||
*/
|
||||
int32_t CP0_Count;
|
||||
/*
|
||||
* CP0 Register 10
|
||||
*/
|
||||
target_ulong CP0_EntryHi;
|
||||
#define CP0EnHi_EHINV 10
|
||||
target_ulong CP0_EntryHi_ASID_mask;
|
||||
/*
|
||||
* CP0 Register 11
|
||||
*/
|
||||
int32_t CP0_Compare;
|
||||
/*
|
||||
* CP0 Register 12
|
||||
*/
|
||||
int32_t CP0_Status;
|
||||
#define CP0St_CU3 31
|
||||
#define CP0St_CU2 30
|
||||
|
|
@ -480,6 +519,9 @@ struct CPUMIPSState {
|
|||
#define CP0SRSMap_SSV2 8
|
||||
#define CP0SRSMap_SSV1 4
|
||||
#define CP0SRSMap_SSV0 0
|
||||
/*
|
||||
* CP0 Register 13
|
||||
*/
|
||||
int32_t CP0_Cause;
|
||||
#define CP0Ca_BD 31
|
||||
#define CP0Ca_TI 30
|
||||
|
|
@ -491,12 +533,21 @@ struct CPUMIPSState {
|
|||
#define CP0Ca_IP 8
|
||||
#define CP0Ca_IP_mask 0x0000FF00
|
||||
#define CP0Ca_EC 2
|
||||
/*
|
||||
* CP0 Register 14
|
||||
*/
|
||||
target_ulong CP0_EPC;
|
||||
/*
|
||||
* CP0 Register 15
|
||||
*/
|
||||
int32_t CP0_PRid;
|
||||
target_ulong CP0_EBase;
|
||||
target_ulong CP0_EBaseWG_rw_bitmask;
|
||||
#define CP0EBase_WG 11
|
||||
target_ulong CP0_CMGCRBase;
|
||||
/*
|
||||
* CP0 Register 16
|
||||
*/
|
||||
int32_t CP0_Config0;
|
||||
#define CP0C0_M 31
|
||||
#define CP0C0_K23 28 /* 30..28 */
|
||||
|
|
@ -612,6 +663,9 @@ struct CPUMIPSState {
|
|||
int32_t CP0_Config7;
|
||||
uint64_t CP0_MAAR[MIPS_MAAR_MAX];
|
||||
int32_t CP0_MAARI;
|
||||
/*
|
||||
* CP0 Register 17
|
||||
*/
|
||||
/* XXX: Maybe make LLAddr per-TC? */
|
||||
uint64_t lladdr;
|
||||
target_ulong llval;
|
||||
|
|
@ -621,11 +675,23 @@ struct CPUMIPSState {
|
|||
target_ulong llreg;
|
||||
uint64_t CP0_LLAddr_rw_bitmask;
|
||||
int CP0_LLAddr_shift;
|
||||
/*
|
||||
* CP0 Register 18
|
||||
*/
|
||||
target_ulong CP0_WatchLo[8];
|
||||
/*
|
||||
* CP0 Register 19
|
||||
*/
|
||||
int32_t CP0_WatchHi[8];
|
||||
#define CP0WH_ASID 16
|
||||
/*
|
||||
* CP0 Register 20
|
||||
*/
|
||||
target_ulong CP0_XContext;
|
||||
int32_t CP0_Framemask;
|
||||
/*
|
||||
* CP0 Register 23
|
||||
*/
|
||||
int32_t CP0_Debug;
|
||||
#define CP0DB_DBD 31
|
||||
#define CP0DB_DM 30
|
||||
|
|
@ -645,17 +711,38 @@ struct CPUMIPSState {
|
|||
#define CP0DB_DDBL 2
|
||||
#define CP0DB_DBp 1
|
||||
#define CP0DB_DSS 0
|
||||
/*
|
||||
* CP0 Register 24
|
||||
*/
|
||||
target_ulong CP0_DEPC;
|
||||
/*
|
||||
* CP0 Register 25
|
||||
*/
|
||||
int32_t CP0_Performance0;
|
||||
/*
|
||||
* CP0 Register 26
|
||||
*/
|
||||
int32_t CP0_ErrCtl;
|
||||
#define CP0EC_WST 29
|
||||
#define CP0EC_SPR 28
|
||||
#define CP0EC_ITC 26
|
||||
/*
|
||||
* CP0 Register 28
|
||||
*/
|
||||
uint64_t CP0_TagLo;
|
||||
int32_t CP0_DataLo;
|
||||
/*
|
||||
* CP0 Register 29
|
||||
*/
|
||||
int32_t CP0_TagHi;
|
||||
int32_t CP0_DataHi;
|
||||
/*
|
||||
* CP0 Register 30
|
||||
*/
|
||||
target_ulong CP0_ErrorEPC;
|
||||
/*
|
||||
* CP0 Register 31
|
||||
*/
|
||||
int32_t CP0_DESAVE;
|
||||
/* We waste some space so we can handle shadow registers like TCs. */
|
||||
TCState tcs[MIPS_SHADOW_SET_MAX];
|
||||
|
|
|
|||
Loading…
Reference in a new issue