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target/arm: Use new FPCR_NZCV_MASK constant

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We defined a constant name for the mask of NZCV bits in the FPCR/FPSCR
in the previous commit; use it in a couple of places in existing code,
where we're masking out everything except NZCV for the "load to Rt=15
sets CPSR.NZCV" special case.

Backports 6a017acdf83e3bb6bd5e85289ca90b2ea3282b7e
This commit is contained in:
Peter Maydell 2021-03-03 18:47:28 -05:00 committed by Lioncash
parent 2c6e54d1cd
commit 2de945ba4d
1 changed files with 2 additions and 2 deletions
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4
qemu/target/arm/translate-vfp.inc.c
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@ -754,7 +754,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
* helper call for the "VMRS to CPSR.NZCV" insn.
*/
tmp = load_cpu_field(s, vfp.xregs[ARM_VFP_FPSCR]);
tcg_gen_andi_i32(tcg_ctx, tmp, tmp, 0xf0000000);
tcg_gen_andi_i32(tcg_ctx, tmp, tmp, FPCR_NZCV_MASK);
storefn(s, opaque, tmp);
break;
default:
@ -897,7 +897,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
case ARM_VFP_FPSCR:
if (a->rt == 15) {
tmp = load_cpu_field(s, vfp.xregs[ARM_VFP_FPSCR]);
tcg_gen_andi_i32(tcg_ctx, tmp, tmp, 0xf0000000);
tcg_gen_andi_i32(tcg_ctx, tmp, tmp, FPCR_NZCV_MASK);
} else {
tmp = tcg_temp_new_i32(tcg_ctx);
gen_helper_vfp_get_fpscr(tcg_ctx, tmp, tcg_ctx->cpu_env);