target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn

Use the "normal" memory access functions, rather than the
softmmu internal helper functions directly.

Since fb901c9, cpu_mem_index is now a simple extract
from env->hflags and not a large computation.  Which means
that it's now more work to pass around this value than it
is to recompute it.

This only adjusts the primitives, and does not clean up
all of the uses within sve_helper.c.

qemu/aarch64.h

@@ -303,6 +303,61 @@
 #define cpu_ldl_code cpu_ldl_code_aarch64
 #define cpu_ldub_code cpu_ldub_code_aarch64
 #define cpu_lduw_code cpu_lduw_code_aarch64
+#define cpu_ldub_code cpu_ldub_code_aarch64
+#define cpu_lduw_code cpu_lduw_code_aarch64
+#define cpu_ldl_code cpu_ldl_code_aarch64
+#define cpu_ldq_code cpu_ldq_code_aarch64
+#define cpu_ldub_mmuidx_ra cpu_ldub_mmuidx_ra_aarch64
+#define cpu_ldsb_mmuidx_ra cpu_ldsb_mmuidx_ra_aarch64
+#define cpu_lduw_be_mmuidx_ra cpu_lduw_be_mmuidx_ra_aarch64
+#define cpu_ldsw_be_mmuidx_ra cpu_ldsw_be_mmuidx_ra_aarch64
+#define cpu_ldl_be_mmuidx_ra cpu_ldl_be_mmuidx_ra_aarch64
+#define cpu_ldq_be_mmuidx_ra cpu_ldq_be_mmuidx_ra_aarch64
+#define cpu_lduw_le_mmuidx_ra cpu_lduw_le_mmuidx_ra_aarch64
+#define cpu_ldsw_le_mmuidx_ra cpu_ldsw_le_mmuidx_ra_aarch64
+#define cpu_ldl_le_mmuidx_ra cpu_ldl_le_mmuidx_ra_aarch64
+#define cpu_ldq_le_mmuidx_ra cpu_ldq_le_mmuidx_ra_aarch64
+#define cpu_stb_mmuidx_ra cpu_stb_mmuidx_ra_aarch64
+#define cpu_stw_be_mmuidx_ra cpu_stw_be_mmuidx_ra_aarch64
+#define cpu_stl_be_mmuidx_ra cpu_stl_be_mmuidx_ra_aarch64
+#define cpu_stq_be_mmuidx_ra cpu_stq_be_mmuidx_ra_aarch64
+#define cpu_stw_le_mmuidx_ra cpu_stw_le_mmuidx_ra_aarch64
+#define cpu_stl_le_mmuidx_ra cpu_stl_le_mmuidx_ra_aarch64
+#define cpu_stq_le_mmuidx_ra cpu_stq_le_mmuidx_ra_aarch64
+#define cpu_ldub_data cpu_ldub_data_aarch64
+#define cpu_ldsb_data cpu_ldsb_data_aarch64
+#define cpu_lduw_be_data cpu_lduw_be_data_aarch64
+#define cpu_ldsw_be_data cpu_ldsw_be_data_aarch64
+#define cpu_ldl_be_data cpu_ldl_be_data_aarch64
+#define cpu_ldq_be_data cpu_ldq_be_data_aarch64
+#define cpu_lduw_le_data cpu_lduw_le_data_aarch64
+#define cpu_ldsw_le_data cpu_ldsw_le_data_aarch64
+#define cpu_ldl_le_data cpu_ldl_le_data_aarch64
+#define cpu_ldq_le_data cpu_ldq_le_data_aarch64
+#define cpu_ldub_data_ra cpu_ldub_data_ra_aarch64
+#define cpu_ldsb_data_ra cpu_ldsb_data_ra_aarch64
+#define cpu_lduw_be_data_ra cpu_lduw_be_data_ra_aarch64
+#define cpu_ldsw_be_data_ra cpu_ldsw_be_data_ra_aarch64
+#define cpu_ldl_be_data_ra cpu_ldl_be_data_ra_aarch64
+#define cpu_ldq_be_data_ra cpu_ldq_be_data_ra_aarch64
+#define cpu_lduw_le_data_ra cpu_lduw_le_data_ra_aarch64
+#define cpu_ldsw_le_data_ra cpu_ldsw_le_data_ra_aarch64
+#define cpu_ldl_le_data_ra cpu_ldl_le_data_ra_aarch64
+#define cpu_ldq_le_data_ra cpu_ldq_le_data_ra_aarch64
+#define cpu_stb_data cpu_stb_data_aarch64
+#define cpu_stw_be_data cpu_stw_be_data_aarch64
+#define cpu_stl_be_data cpu_stl_be_data_aarch64
+#define cpu_stq_be_data cpu_stq_be_data_aarch64
+#define cpu_stw_le_data cpu_stw_le_data_aarch64
+#define cpu_stl_le_data cpu_stl_le_data_aarch64
+#define cpu_stq_le_data cpu_stq_le_data_aarch64
+#define cpu_stb_data_ra cpu_stb_data_ra_aarch64
+#define cpu_stw_be_data_ra cpu_stw_be_data_ra_aarch64
+#define cpu_stl_be_data_ra cpu_stl_be_data_ra_aarch64
+#define cpu_stq_be_data_ra cpu_stq_be_data_ra_aarch64
+#define cpu_stw_le_data_ra cpu_stw_le_data_ra_aarch64
+#define cpu_stl_le_data_ra cpu_stl_le_data_ra_aarch64
+#define cpu_stq_le_data_ra cpu_stq_le_data_ra_aarch64
 #define cpu_loop_exit cpu_loop_exit_aarch64
 #define cpu_loop_exit_atomic cpu_loop_exit_atomic_aarch64
 #define cpu_loop_exit_noexc cpu_loop_exit_noexc_aarch64

qemu/aarch64eb.h

@@ -303,6 +303,61 @@
 #define cpu_ldl_code cpu_ldl_code_aarch64eb
 #define cpu_ldub_code cpu_ldub_code_aarch64eb
 #define cpu_lduw_code cpu_lduw_code_aarch64eb
+#define cpu_ldub_code cpu_ldub_code_aarch64eb
+#define cpu_lduw_code cpu_lduw_code_aarch64eb
+#define cpu_ldl_code cpu_ldl_code_aarch64eb
+#define cpu_ldq_code cpu_ldq_code_aarch64eb
+#define cpu_ldub_mmuidx_ra cpu_ldub_mmuidx_ra_aarch64eb
+#define cpu_ldsb_mmuidx_ra cpu_ldsb_mmuidx_ra_aarch64eb
+#define cpu_lduw_be_mmuidx_ra cpu_lduw_be_mmuidx_ra_aarch64eb
+#define cpu_ldsw_be_mmuidx_ra cpu_ldsw_be_mmuidx_ra_aarch64eb
+#define cpu_ldl_be_mmuidx_ra cpu_ldl_be_mmuidx_ra_aarch64eb
+#define cpu_ldq_be_mmuidx_ra cpu_ldq_be_mmuidx_ra_aarch64eb
+#define cpu_lduw_le_mmuidx_ra cpu_lduw_le_mmuidx_ra_aarch64eb
+#define cpu_ldsw_le_mmuidx_ra cpu_ldsw_le_mmuidx_ra_aarch64eb
+#define cpu_ldl_le_mmuidx_ra cpu_ldl_le_mmuidx_ra_aarch64eb
+#define cpu_ldq_le_mmuidx_ra cpu_ldq_le_mmuidx_ra_aarch64eb
+#define cpu_stb_mmuidx_ra cpu_stb_mmuidx_ra_aarch64eb
+#define cpu_stw_be_mmuidx_ra cpu_stw_be_mmuidx_ra_aarch64eb
+#define cpu_stl_be_mmuidx_ra cpu_stl_be_mmuidx_ra_aarch64eb
+#define cpu_stq_be_mmuidx_ra cpu_stq_be_mmuidx_ra_aarch64eb
+#define cpu_stw_le_mmuidx_ra cpu_stw_le_mmuidx_ra_aarch64eb
+#define cpu_stl_le_mmuidx_ra cpu_stl_le_mmuidx_ra_aarch64eb
+#define cpu_stq_le_mmuidx_ra cpu_stq_le_mmuidx_ra_aarch64eb
+#define cpu_ldub_data cpu_ldub_data_aarch64eb
+#define cpu_ldsb_data cpu_ldsb_data_aarch64eb
+#define cpu_lduw_be_data cpu_lduw_be_data_aarch64eb
+#define cpu_ldsw_be_data cpu_ldsw_be_data_aarch64eb
+#define cpu_ldl_be_data cpu_ldl_be_data_aarch64eb
+#define cpu_ldq_be_data cpu_ldq_be_data_aarch64eb
+#define cpu_lduw_le_data cpu_lduw_le_data_aarch64eb
+#define cpu_ldsw_le_data cpu_ldsw_le_data_aarch64eb
+#define cpu_ldl_le_data cpu_ldl_le_data_aarch64eb
+#define cpu_ldq_le_data cpu_ldq_le_data_aarch64eb
+#define cpu_ldub_data_ra cpu_ldub_data_ra_aarch64eb
+#define cpu_ldsb_data_ra cpu_ldsb_data_ra_aarch64eb
+#define cpu_lduw_be_data_ra cpu_lduw_be_data_ra_aarch64eb
+#define cpu_ldsw_be_data_ra cpu_ldsw_be_data_ra_aarch64eb
+#define cpu_ldl_be_data_ra cpu_ldl_be_data_ra_aarch64eb
+#define cpu_ldq_be_data_ra cpu_ldq_be_data_ra_aarch64eb
+#define cpu_lduw_le_data_ra cpu_lduw_le_data_ra_aarch64eb
+#define cpu_ldsw_le_data_ra cpu_ldsw_le_data_ra_aarch64eb
+#define cpu_ldl_le_data_ra cpu_ldl_le_data_ra_aarch64eb
+#define cpu_ldq_le_data_ra cpu_ldq_le_data_ra_aarch64eb
+#define cpu_stb_data cpu_stb_data_aarch64eb
+#define cpu_stw_be_data cpu_stw_be_data_aarch64eb
+#define cpu_stl_be_data cpu_stl_be_data_aarch64eb
+#define cpu_stq_be_data cpu_stq_be_data_aarch64eb
+#define cpu_stw_le_data cpu_stw_le_data_aarch64eb
+#define cpu_stl_le_data cpu_stl_le_data_aarch64eb
+#define cpu_stq_le_data cpu_stq_le_data_aarch64eb
+#define cpu_stb_data_ra cpu_stb_data_ra_aarch64eb
+#define cpu_stw_be_data_ra cpu_stw_be_data_ra_aarch64eb
+#define cpu_stl_be_data_ra cpu_stl_be_data_ra_aarch64eb
+#define cpu_stq_be_data_ra cpu_stq_be_data_ra_aarch64eb
+#define cpu_stw_le_data_ra cpu_stw_le_data_ra_aarch64eb
+#define cpu_stl_le_data_ra cpu_stl_le_data_ra_aarch64eb
+#define cpu_stq_le_data_ra cpu_stq_le_data_ra_aarch64eb
 #define cpu_loop_exit cpu_loop_exit_aarch64eb
 #define cpu_loop_exit_atomic cpu_loop_exit_atomic_aarch64eb
 #define cpu_loop_exit_noexc cpu_loop_exit_noexc_aarch64eb

qemu/accel/tcg/cputlb.c

@@ -908,8 +908,7 @@ typedef uint64_t FullLoadHelper(CPUArchState *env, target_ulong addr,
 
 static inline uint64_t __attribute__((always_inline))
 load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
-            uintptr_t retaddr, MemOp op, bool code_read, bool is_softmmu_access,
+            uintptr_t retaddr, MemOp op, bool code_read, FullLoadHelper *full_load)
-            FullLoadHelper *full_load)
 {
     uintptr_t mmu_idx = get_mmuidx(oi);
     uintptr_t index = tlb_index(env, mmu_idx, addr);
@@ -934,27 +933,17 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
     // memory might be still unmapped while reading or fetching
     if (mr == NULL) {
         handled = false;
-        if (is_softmmu_access) {
+
-            error_code = UC_ERR_FETCH_UNMAPPED;
+        error_code = UC_ERR_READ_UNMAPPED;
-            HOOK_FOREACH(uc, hook, UC_HOOK_MEM_FETCH_UNMAPPED) {
+        HOOK_FOREACH(uc, hook, UC_HOOK_MEM_READ_UNMAPPED) {
-                if (!HOOK_BOUND_CHECK(hook, addr)) {
+            if (!HOOK_BOUND_CHECK(hook, addr)) {
-                    continue;
+                continue;
-                }
-                if ((handled = ((uc_cb_eventmem_t)hook->callback)(uc, UC_MEM_FETCH_UNMAPPED, addr, size, 0, hook->user_data))) {
-                    break;
-                }
             }
-        } else {
+            if ((handled = ((uc_cb_eventmem_t)hook->callback)(uc, UC_MEM_READ_UNMAPPED, addr, size, 0, hook->user_data))) {
-            error_code = UC_ERR_READ_UNMAPPED;
+                break;
-            HOOK_FOREACH(uc, hook, UC_HOOK_MEM_READ_UNMAPPED) {
-                if (!HOOK_BOUND_CHECK(hook, addr)) {
-                    continue;
-                }
-                if ((handled = ((uc_cb_eventmem_t)hook->callback)(uc, UC_MEM_READ_UNMAPPED, addr, size, 0, hook->user_data))) {
-                    break;
-                }
             }
         }
+
         if (handled) {
             env->invalid_error = UC_ERR_OK;
             mr = memory_mapping(uc, addr);  // FIXME: what if mr is still NULL at this time?
@@ -967,28 +956,26 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
         }
     }
 
-    if (is_softmmu_access) {
+    // Unicorn: callback on fetch from NX
-        // Unicorn: callback on fetch from NX
+    if (mr != NULL && !(mr->perms & UC_PROT_EXEC)) {
-        if (mr != NULL && !(mr->perms & UC_PROT_EXEC)) {
+        handled = false;
-            handled = false;
+        HOOK_FOREACH(uc, hook, UC_HOOK_MEM_FETCH_PROT) {
-            HOOK_FOREACH(uc, hook, UC_HOOK_MEM_FETCH_PROT) {
+            if (!HOOK_BOUND_CHECK(hook, addr)) {
-                if (!HOOK_BOUND_CHECK(hook, addr)) {
+                continue;
-                    continue;
-                }
-                if ((handled = ((uc_cb_eventmem_t)hook->callback)(uc, UC_MEM_FETCH_PROT, addr, size, 0, hook->user_data))) {
-                    break;
-                }
             }
+            if ((handled = ((uc_cb_eventmem_t)hook->callback)(uc, UC_MEM_FETCH_PROT, addr, size, 0, hook->user_data))) {
+                break;
+            }
+        }
 
-            if (handled) {
+        if (handled) {
-                env->invalid_error = UC_ERR_OK;
+            env->invalid_error = UC_ERR_OK;
-            } else {
+        } else {
-                env->invalid_addr = addr;
+            env->invalid_addr = addr;
-                env->invalid_error = UC_ERR_FETCH_PROT;
+            env->invalid_error = UC_ERR_FETCH_PROT;
-                // printf("***** Invalid fetch (non-executable) at " TARGET_FMT_lx "\n", addr);
+            // printf("***** Invalid fetch (non-executable) at " TARGET_FMT_lx "\n", addr);
-                cpu_exit(uc->current_cpu);
+            cpu_exit(uc->current_cpu);
-                return 0;
+            return 0;
-            }
         }
     }
 
@@ -1157,7 +1144,7 @@ finished:
 static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong addr,
                               TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, MO_UB, false, false,
+    return load_helper(env, addr, oi, retaddr, MO_UB, false,
                        full_ldub_mmu);
 }
 
@@ -1170,7 +1157,7 @@ tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
 static uint64_t full_le_lduw_mmu(CPUArchState *env, target_ulong addr,
                                  TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, MO_LEUW, false, false,
+    return load_helper(env, addr, oi, retaddr, MO_LEUW, false,
                        full_le_lduw_mmu);
 }
 
@@ -1183,7 +1170,7 @@ tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
 static uint64_t full_be_lduw_mmu(CPUArchState *env, target_ulong addr,
                                  TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, MO_BEUW, false, false,
+    return load_helper(env, addr, oi, retaddr, MO_BEUW, false,
                        full_be_lduw_mmu);
 }
 
@@ -1196,7 +1183,7 @@ tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
 static uint64_t full_le_ldul_mmu(CPUArchState *env, target_ulong addr,
                                  TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, MO_LEUL, false, false,
+    return load_helper(env, addr, oi, retaddr, MO_LEUL, false,
                        full_le_ldul_mmu);
 }
 
@@ -1209,7 +1196,7 @@ tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
 static uint64_t full_be_ldul_mmu(CPUArchState *env, target_ulong addr,
                                  TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, MO_BEUL, false, false,
+    return load_helper(env, addr, oi, retaddr, MO_BEUL, false,
                        full_be_ldul_mmu);
 }
 
@@ -1222,14 +1209,14 @@ tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
                            TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, MO_LEQ, false, false,
+    return load_helper(env, addr, oi, retaddr, MO_LEQ, false,
                        helper_le_ldq_mmu);
 }
 
 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
                            TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, MO_BEQ, false, false,
+    return load_helper(env, addr, oi, retaddr, MO_BEQ, false,
                        helper_be_ldq_mmu);
 }
 
@@ -1269,6 +1256,197 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
     return (int32_t)helper_be_ldul_mmu(env, addr, oi, retaddr);
 }
 
+/*
+ * Load helpers for cpu_ldst.h.
+ */
+
+static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr,
+                                       int mmu_idx, uintptr_t retaddr,
+                                       MemOp op, FullLoadHelper *full_load)
+{
+    TCGMemOpIdx oi;
+    uint64_t ret;
+
+    op &= ~MO_SIGN;
+    oi = make_memop_idx(op, mmu_idx);
+    ret = full_load(env, addr, oi, retaddr);
+
+    return ret;
+}
+
+uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                            int mmu_idx, uintptr_t ra)
+{
+    return cpu_load_helper(env, addr, mmu_idx, ra, MO_UB, full_ldub_mmu);
+}
+
+int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                       int mmu_idx, uintptr_t ra)
+{
+    return (int8_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_SB,
+                                   full_ldub_mmu);
+}
+
+uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                               int mmu_idx, uintptr_t ra)
+{
+    return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUW, full_be_lduw_mmu);
+}
+
+int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                          int mmu_idx, uintptr_t ra)
+{
+    return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_BESW,
+                                    full_be_lduw_mmu);
+}
+
+uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                              int mmu_idx, uintptr_t ra)
+{
+    return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUL, full_be_ldul_mmu);
+}
+
+uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                              int mmu_idx, uintptr_t ra)
+{
+    return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEQ, helper_be_ldq_mmu);
+}
+
+uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                               int mmu_idx, uintptr_t ra)
+{
+    return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUW, full_le_lduw_mmu);
+}
+
+int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                          int mmu_idx, uintptr_t ra)
+{
+    return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_LESW,
+                                    full_le_lduw_mmu);
+}
+
+uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                              int mmu_idx, uintptr_t ra)
+{
+    return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUL, full_le_ldul_mmu);
+}
+
+uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                              int mmu_idx, uintptr_t ra)
+{
+    return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEQ, helper_le_ldq_mmu);
+}
+
+//
+
+uint32_t cpu_ldub_data_ra(CPUArchState *env, target_ulong ptr,
+                          uintptr_t retaddr)
+{
+    return cpu_ldub_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
+}
+
+int cpu_ldsb_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
+{
+    return cpu_ldsb_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
+}
+
+uint32_t cpu_lduw_be_data_ra(CPUArchState *env, target_ulong ptr,
+                             uintptr_t retaddr)
+{
+    return cpu_lduw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
+}
+
+int cpu_ldsw_be_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
+{
+    return cpu_ldsw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
+}
+
+uint32_t cpu_ldl_be_data_ra(CPUArchState *env, target_ulong ptr,
+                            uintptr_t retaddr)
+{
+    return cpu_ldl_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
+}
+
+uint64_t cpu_ldq_be_data_ra(CPUArchState *env, target_ulong ptr,
+                            uintptr_t retaddr)
+{
+    return cpu_ldq_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
+}
+
+uint32_t cpu_lduw_le_data_ra(CPUArchState *env, target_ulong ptr,
+                             uintptr_t retaddr)
+{
+    return cpu_lduw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
+}
+
+int cpu_ldsw_le_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
+{
+    return cpu_ldsw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
+}
+
+uint32_t cpu_ldl_le_data_ra(CPUArchState *env, target_ulong ptr,
+                            uintptr_t retaddr)
+{
+    return cpu_ldl_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
+}
+
+uint64_t cpu_ldq_le_data_ra(CPUArchState *env, target_ulong ptr,
+                            uintptr_t retaddr)
+{
+    return cpu_ldq_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
+}
+
+uint32_t cpu_ldub_data(CPUArchState *env, target_ulong ptr)
+{
+    return cpu_ldub_data_ra(env, ptr, 0);
+}
+
+int cpu_ldsb_data(CPUArchState *env, target_ulong ptr)
+{
+    return cpu_ldsb_data_ra(env, ptr, 0);
+}
+
+
+uint32_t cpu_lduw_be_data(CPUArchState *env, target_ulong ptr)
+{
+    return cpu_lduw_be_data_ra(env, ptr, 0);
+}
+
+int cpu_ldsw_be_data(CPUArchState *env, target_ulong ptr)
+{
+    return cpu_ldsw_be_data_ra(env, ptr, 0);
+}
+
+uint32_t cpu_ldl_be_data(CPUArchState *env, target_ulong ptr)
+{
+    return cpu_ldl_be_data_ra(env, ptr, 0);
+}
+
+uint64_t cpu_ldq_be_data(CPUArchState *env, target_ulong ptr)
+{
+    return cpu_ldq_be_data_ra(env, ptr, 0);
+}
+
+uint32_t cpu_lduw_le_data(CPUArchState *env, target_ulong ptr)
+{
+    return cpu_lduw_le_data_ra(env, ptr, 0);
+}
+
+int cpu_ldsw_le_data(CPUArchState *env, target_ulong ptr)
+{
+    return cpu_ldsw_le_data_ra(env, ptr, 0);
+}
+
+uint32_t cpu_ldl_le_data(CPUArchState *env, target_ulong ptr)
+{
+    return cpu_ldl_le_data_ra(env, ptr, 0);
+}
+
+uint64_t cpu_ldq_le_data(CPUArchState *env, target_ulong ptr)
+{
+    return cpu_ldq_le_data_ra(env, ptr, 0);
+}
+
 /*
  * Store Helpers
  */
@@ -1548,6 +1726,119 @@ void cpu_stb_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
     cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_UB);
 }
 
+void cpu_stw_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
+                          int mmu_idx, uintptr_t retaddr)
+{
+    cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUW);
+}
+
+void cpu_stl_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
+                          int mmu_idx, uintptr_t retaddr)
+{
+    cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUL);
+}
+
+void cpu_stq_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
+                          int mmu_idx, uintptr_t retaddr)
+{
+    cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEQ);
+}
+
+void cpu_stw_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
+                          int mmu_idx, uintptr_t retaddr)
+{
+    cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUW);
+}
+
+void cpu_stl_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
+                          int mmu_idx, uintptr_t retaddr)
+{
+    cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUL);
+}
+
+void cpu_stq_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
+                          int mmu_idx, uintptr_t retaddr)
+{
+    cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEQ);
+}
+
+void cpu_stb_data_ra(CPUArchState *env, target_ulong ptr,
+                     uint32_t val, uintptr_t retaddr)
+{
+    cpu_stb_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
+}
+
+void cpu_stw_be_data_ra(CPUArchState *env, target_ulong ptr,
+                        uint32_t val, uintptr_t retaddr)
+{
+    cpu_stw_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
+}
+
+void cpu_stl_be_data_ra(CPUArchState *env, target_ulong ptr,
+                        uint32_t val, uintptr_t retaddr)
+{
+    cpu_stl_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
+}
+
+void cpu_stq_be_data_ra(CPUArchState *env, target_ulong ptr,
+                        uint64_t val, uintptr_t retaddr)
+{
+    cpu_stq_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
+}
+
+void cpu_stw_le_data_ra(CPUArchState *env, target_ulong ptr,
+                        uint32_t val, uintptr_t retaddr)
+{
+    cpu_stw_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
+}
+
+void cpu_stl_le_data_ra(CPUArchState *env, target_ulong ptr,
+                        uint32_t val, uintptr_t retaddr)
+{
+    cpu_stl_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
+}
+
+void cpu_stq_le_data_ra(CPUArchState *env, target_ulong ptr,
+                        uint64_t val, uintptr_t retaddr)
+{
+    cpu_stq_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
+}
+
+void cpu_stb_data(CPUArchState *env, target_ulong ptr, uint32_t val)
+{
+    cpu_stb_data_ra(env, ptr, val, 0);
+}
+
+void cpu_stw_be_data(CPUArchState *env, target_ulong ptr, uint32_t val)
+{
+    cpu_stw_be_data_ra(env, ptr, val, 0);
+}
+
+void cpu_stl_be_data(CPUArchState *env, target_ulong ptr, uint32_t val)
+{
+    cpu_stl_be_data_ra(env, ptr, val, 0);
+}
+
+void cpu_stq_be_data(CPUArchState *env, target_ulong ptr, uint64_t val)
+{
+    cpu_stq_be_data_ra(env, ptr, val, 0);
+}
+
+void cpu_stw_le_data(CPUArchState *env, target_ulong ptr, uint32_t val)
+{
+    cpu_stw_le_data_ra(env, ptr, val, 0);
+}
+
+void cpu_stl_le_data(CPUArchState *env, target_ulong ptr, uint32_t val)
+{
+    cpu_stl_le_data_ra(env, ptr, val, 0);
+}
+
+void cpu_stq_le_data(CPUArchState *env, target_ulong ptr, uint64_t val)
+{
+    cpu_stq_le_data_ra(env, ptr, val, 0);
+}
+
 /* First set of helpers allows passing in of OI and RETADDR.  This makes
    them callable from other helpers.  */
 
@@ -1601,10 +1892,58 @@ void cpu_stb_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
 
 /* Code access functions.  */
 
+static uint64_t full_ldub_code(CPUArchState *env, target_ulong addr,
+                               TCGMemOpIdx oi, uintptr_t retaddr)
+{
+    return load_helper(env, addr, oi, retaddr, MO_8, true, full_ldub_code);
+}
+
+uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr)
+{
+    TCGMemOpIdx oi = make_memop_idx(MO_UB, cpu_mmu_index(env, true));
+    return full_ldub_code(env, addr, oi, 0);
+}
+
+static uint64_t full_lduw_code(CPUArchState *env, target_ulong addr,
+                               TCGMemOpIdx oi, uintptr_t retaddr)
+{
+    return load_helper(env, addr, oi, retaddr, MO_TEUW, true, full_lduw_code);
+}
+
+uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr)
+{
+    TCGMemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(env, true));
+    return full_lduw_code(env, addr, oi, 0);
+}
+
+static uint64_t full_ldl_code(CPUArchState *env, target_ulong addr,
+                              TCGMemOpIdx oi, uintptr_t retaddr)
+{
+    return load_helper(env, addr, oi, retaddr, MO_TEUL, true, full_ldl_code);
+}
+
+uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr)
+{
+    TCGMemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(env, true));
+    return full_ldl_code(env, addr, oi, 0);
+}
+
+static uint64_t full_ldq_code(CPUArchState *env, target_ulong addr,
+                              TCGMemOpIdx oi, uintptr_t retaddr)
+{
+    return load_helper(env, addr, oi, retaddr, MO_TEQ, true, full_ldq_code);
+}
+
+uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr)
+{
+    TCGMemOpIdx oi = make_memop_idx(MO_TEQ, cpu_mmu_index(env, true));
+    return full_ldq_code(env, addr, oi, 0);
+}
+
 static uint64_t full_ldub_cmmu(CPUArchState *env, target_ulong addr,
                                TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, MO_8, true, true, full_ldub_cmmu);
+    return load_helper(env, addr, oi, retaddr, MO_8, true, full_ldub_cmmu);
 }
 
 uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
@@ -1616,7 +1955,7 @@ uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
 static uint64_t full_le_lduw_cmmu(CPUArchState *env, target_ulong addr,
                                   TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, MO_LEUW, true, true,
+    return load_helper(env, addr, oi, retaddr, MO_LEUW, true,
                        full_le_lduw_cmmu);
 }
 
@@ -1629,7 +1968,7 @@ uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
 static uint64_t full_be_lduw_cmmu(CPUArchState *env, target_ulong addr,
                                   TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, MO_BEUW, true, true,
+    return load_helper(env, addr, oi, retaddr, MO_BEUW, true,
                        full_be_lduw_cmmu);
 }
 
@@ -1642,7 +1981,7 @@ uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
 static uint64_t full_le_ldul_cmmu(CPUArchState *env, target_ulong addr,
                                   TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, MO_LEUL, true, true,
+    return load_helper(env, addr, oi, retaddr, MO_LEUL, true,
                        full_le_ldul_cmmu);
 }
 
@@ -1655,7 +1994,7 @@ uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
 static uint64_t full_be_ldul_cmmu(CPUArchState *env, target_ulong addr,
                                   TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, MO_BEUL, true, true,
+    return load_helper(env, addr, oi, retaddr, MO_BEUL, true,
                        full_be_ldul_cmmu);
 }
 
@@ -1668,13 +2007,13 @@ uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
 uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
                             TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, MO_LEQ, true, true,
+    return load_helper(env, addr, oi, retaddr, MO_LEQ, true,
                        helper_le_ldq_cmmu);
 }
 
 uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
                             TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, MO_BEQ, true, true,
+    return load_helper(env, addr, oi, retaddr, MO_BEQ, true,
                        helper_be_ldq_cmmu);
 }

qemu/arm.h

@@ -303,6 +303,61 @@
 #define cpu_ldl_code cpu_ldl_code_arm
 #define cpu_ldub_code cpu_ldub_code_arm
 #define cpu_lduw_code cpu_lduw_code_arm
+#define cpu_ldub_code cpu_ldub_code_arm
+#define cpu_lduw_code cpu_lduw_code_arm
+#define cpu_ldl_code cpu_ldl_code_arm
+#define cpu_ldq_code cpu_ldq_code_arm
+#define cpu_ldub_mmuidx_ra cpu_ldub_mmuidx_ra_arm
+#define cpu_ldsb_mmuidx_ra cpu_ldsb_mmuidx_ra_arm
+#define cpu_lduw_be_mmuidx_ra cpu_lduw_be_mmuidx_ra_arm
+#define cpu_ldsw_be_mmuidx_ra cpu_ldsw_be_mmuidx_ra_arm
+#define cpu_ldl_be_mmuidx_ra cpu_ldl_be_mmuidx_ra_arm
+#define cpu_ldq_be_mmuidx_ra cpu_ldq_be_mmuidx_ra_arm
+#define cpu_lduw_le_mmuidx_ra cpu_lduw_le_mmuidx_ra_arm
+#define cpu_ldsw_le_mmuidx_ra cpu_ldsw_le_mmuidx_ra_arm
+#define cpu_ldl_le_mmuidx_ra cpu_ldl_le_mmuidx_ra_arm
+#define cpu_ldq_le_mmuidx_ra cpu_ldq_le_mmuidx_ra_arm
+#define cpu_stb_mmuidx_ra cpu_stb_mmuidx_ra_arm
+#define cpu_stw_be_mmuidx_ra cpu_stw_be_mmuidx_ra_arm
+#define cpu_stl_be_mmuidx_ra cpu_stl_be_mmuidx_ra_arm
+#define cpu_stq_be_mmuidx_ra cpu_stq_be_mmuidx_ra_arm
+#define cpu_stw_le_mmuidx_ra cpu_stw_le_mmuidx_ra_arm
+#define cpu_stl_le_mmuidx_ra cpu_stl_le_mmuidx_ra_arm
+#define cpu_stq_le_mmuidx_ra cpu_stq_le_mmuidx_ra_arm
+#define cpu_ldub_data cpu_ldub_data_arm
+#define cpu_ldsb_data cpu_ldsb_data_arm
+#define cpu_lduw_be_data cpu_lduw_be_data_arm
+#define cpu_ldsw_be_data cpu_ldsw_be_data_arm
+#define cpu_ldl_be_data cpu_ldl_be_data_arm
+#define cpu_ldq_be_data cpu_ldq_be_data_arm
+#define cpu_lduw_le_data cpu_lduw_le_data_arm
+#define cpu_ldsw_le_data cpu_ldsw_le_data_arm
+#define cpu_ldl_le_data cpu_ldl_le_data_arm
+#define cpu_ldq_le_data cpu_ldq_le_data_arm
+#define cpu_ldub_data_ra cpu_ldub_data_ra_arm
+#define cpu_ldsb_data_ra cpu_ldsb_data_ra_arm
+#define cpu_lduw_be_data_ra cpu_lduw_be_data_ra_arm
+#define cpu_ldsw_be_data_ra cpu_ldsw_be_data_ra_arm
+#define cpu_ldl_be_data_ra cpu_ldl_be_data_ra_arm
+#define cpu_ldq_be_data_ra cpu_ldq_be_data_ra_arm
+#define cpu_lduw_le_data_ra cpu_lduw_le_data_ra_arm
+#define cpu_ldsw_le_data_ra cpu_ldsw_le_data_ra_arm
+#define cpu_ldl_le_data_ra cpu_ldl_le_data_ra_arm
+#define cpu_ldq_le_data_ra cpu_ldq_le_data_ra_arm
+#define cpu_stb_data cpu_stb_data_arm
+#define cpu_stw_be_data cpu_stw_be_data_arm
+#define cpu_stl_be_data cpu_stl_be_data_arm
+#define cpu_stq_be_data cpu_stq_be_data_arm
+#define cpu_stw_le_data cpu_stw_le_data_arm
+#define cpu_stl_le_data cpu_stl_le_data_arm
+#define cpu_stq_le_data cpu_stq_le_data_arm
+#define cpu_stb_data_ra cpu_stb_data_ra_arm
+#define cpu_stw_be_data_ra cpu_stw_be_data_ra_arm
+#define cpu_stl_be_data_ra cpu_stl_be_data_ra_arm
+#define cpu_stq_be_data_ra cpu_stq_be_data_ra_arm
+#define cpu_stw_le_data_ra cpu_stw_le_data_ra_arm
+#define cpu_stl_le_data_ra cpu_stl_le_data_ra_arm
+#define cpu_stq_le_data_ra cpu_stq_le_data_ra_arm
 #define cpu_loop_exit cpu_loop_exit_arm
 #define cpu_loop_exit_atomic cpu_loop_exit_atomic_arm
 #define cpu_loop_exit_noexc cpu_loop_exit_noexc_arm

qemu/armeb.h

@@ -303,6 +303,61 @@
 #define cpu_ldl_code cpu_ldl_code_armeb
 #define cpu_ldub_code cpu_ldub_code_armeb
 #define cpu_lduw_code cpu_lduw_code_armeb
+#define cpu_ldub_code cpu_ldub_code_armeb
+#define cpu_lduw_code cpu_lduw_code_armeb
+#define cpu_ldl_code cpu_ldl_code_armeb
+#define cpu_ldq_code cpu_ldq_code_armeb
+#define cpu_ldub_mmuidx_ra cpu_ldub_mmuidx_ra_armeb
+#define cpu_ldsb_mmuidx_ra cpu_ldsb_mmuidx_ra_armeb
+#define cpu_lduw_be_mmuidx_ra cpu_lduw_be_mmuidx_ra_armeb
+#define cpu_ldsw_be_mmuidx_ra cpu_ldsw_be_mmuidx_ra_armeb
+#define cpu_ldl_be_mmuidx_ra cpu_ldl_be_mmuidx_ra_armeb
+#define cpu_ldq_be_mmuidx_ra cpu_ldq_be_mmuidx_ra_armeb
+#define cpu_lduw_le_mmuidx_ra cpu_lduw_le_mmuidx_ra_armeb
+#define cpu_ldsw_le_mmuidx_ra cpu_ldsw_le_mmuidx_ra_armeb
+#define cpu_ldl_le_mmuidx_ra cpu_ldl_le_mmuidx_ra_armeb
+#define cpu_ldq_le_mmuidx_ra cpu_ldq_le_mmuidx_ra_armeb
+#define cpu_stb_mmuidx_ra cpu_stb_mmuidx_ra_armeb
+#define cpu_stw_be_mmuidx_ra cpu_stw_be_mmuidx_ra_armeb
+#define cpu_stl_be_mmuidx_ra cpu_stl_be_mmuidx_ra_armeb
+#define cpu_stq_be_mmuidx_ra cpu_stq_be_mmuidx_ra_armeb
+#define cpu_stw_le_mmuidx_ra cpu_stw_le_mmuidx_ra_armeb
+#define cpu_stl_le_mmuidx_ra cpu_stl_le_mmuidx_ra_armeb
+#define cpu_stq_le_mmuidx_ra cpu_stq_le_mmuidx_ra_armeb
+#define cpu_ldub_data cpu_ldub_data_armeb
+#define cpu_ldsb_data cpu_ldsb_data_armeb
+#define cpu_lduw_be_data cpu_lduw_be_data_armeb
+#define cpu_ldsw_be_data cpu_ldsw_be_data_armeb
+#define cpu_ldl_be_data cpu_ldl_be_data_armeb
+#define cpu_ldq_be_data cpu_ldq_be_data_armeb
+#define cpu_lduw_le_data cpu_lduw_le_data_armeb
+#define cpu_ldsw_le_data cpu_ldsw_le_data_armeb
+#define cpu_ldl_le_data cpu_ldl_le_data_armeb
+#define cpu_ldq_le_data cpu_ldq_le_data_armeb
+#define cpu_ldub_data_ra cpu_ldub_data_ra_armeb
+#define cpu_ldsb_data_ra cpu_ldsb_data_ra_armeb
+#define cpu_lduw_be_data_ra cpu_lduw_be_data_ra_armeb
+#define cpu_ldsw_be_data_ra cpu_ldsw_be_data_ra_armeb
+#define cpu_ldl_be_data_ra cpu_ldl_be_data_ra_armeb
+#define cpu_ldq_be_data_ra cpu_ldq_be_data_ra_armeb
+#define cpu_lduw_le_data_ra cpu_lduw_le_data_ra_armeb
+#define cpu_ldsw_le_data_ra cpu_ldsw_le_data_ra_armeb
+#define cpu_ldl_le_data_ra cpu_ldl_le_data_ra_armeb
+#define cpu_ldq_le_data_ra cpu_ldq_le_data_ra_armeb
+#define cpu_stb_data cpu_stb_data_armeb
+#define cpu_stw_be_data cpu_stw_be_data_armeb
+#define cpu_stl_be_data cpu_stl_be_data_armeb
+#define cpu_stq_be_data cpu_stq_be_data_armeb
+#define cpu_stw_le_data cpu_stw_le_data_armeb
+#define cpu_stl_le_data cpu_stl_le_data_armeb
+#define cpu_stq_le_data cpu_stq_le_data_armeb
+#define cpu_stb_data_ra cpu_stb_data_ra_armeb
+#define cpu_stw_be_data_ra cpu_stw_be_data_ra_armeb
+#define cpu_stl_be_data_ra cpu_stl_be_data_ra_armeb
+#define cpu_stq_be_data_ra cpu_stq_be_data_ra_armeb
+#define cpu_stw_le_data_ra cpu_stw_le_data_ra_armeb
+#define cpu_stl_le_data_ra cpu_stl_le_data_ra_armeb
+#define cpu_stq_le_data_ra cpu_stq_le_data_ra_armeb
 #define cpu_loop_exit cpu_loop_exit_armeb
 #define cpu_loop_exit_atomic cpu_loop_exit_atomic_armeb
 #define cpu_loop_exit_noexc cpu_loop_exit_noexc_armeb

qemu/header_gen.py

@@ -309,6 +309,61 @@ symbols = (
     'cpu_ldl_code',
     'cpu_ldub_code',
     'cpu_lduw_code',
+    'cpu_ldub_code',
+    'cpu_lduw_code',
+    'cpu_ldl_code',
+    'cpu_ldq_code',
+    'cpu_ldub_mmuidx_ra',
+    'cpu_ldsb_mmuidx_ra',
+    'cpu_lduw_be_mmuidx_ra',
+    'cpu_ldsw_be_mmuidx_ra',
+    'cpu_ldl_be_mmuidx_ra',
+    'cpu_ldq_be_mmuidx_ra',
+    'cpu_lduw_le_mmuidx_ra',
+    'cpu_ldsw_le_mmuidx_ra',
+    'cpu_ldl_le_mmuidx_ra',
+    'cpu_ldq_le_mmuidx_ra',
+    'cpu_stb_mmuidx_ra',
+    'cpu_stw_be_mmuidx_ra',
+    'cpu_stl_be_mmuidx_ra',
+    'cpu_stq_be_mmuidx_ra',
+    'cpu_stw_le_mmuidx_ra',
+    'cpu_stl_le_mmuidx_ra',
+    'cpu_stq_le_mmuidx_ra',
+    'cpu_ldub_data',
+    'cpu_ldsb_data',
+    'cpu_lduw_be_data',
+    'cpu_ldsw_be_data',
+    'cpu_ldl_be_data',
+    'cpu_ldq_be_data',
+    'cpu_lduw_le_data',
+    'cpu_ldsw_le_data',
+    'cpu_ldl_le_data',
+    'cpu_ldq_le_data',
+    'cpu_ldub_data_ra',
+    'cpu_ldsb_data_ra',
+    'cpu_lduw_be_data_ra',
+    'cpu_ldsw_be_data_ra',
+    'cpu_ldl_be_data_ra',
+    'cpu_ldq_be_data_ra',
+    'cpu_lduw_le_data_ra',
+    'cpu_ldsw_le_data_ra',
+    'cpu_ldl_le_data_ra',
+    'cpu_ldq_le_data_ra',
+    'cpu_stb_data',
+    'cpu_stw_be_data',
+    'cpu_stl_be_data',
+    'cpu_stq_be_data',
+    'cpu_stw_le_data',
+    'cpu_stl_le_data',
+    'cpu_stq_le_data',
+    'cpu_stb_data_ra',
+    'cpu_stw_be_data_ra',
+    'cpu_stl_be_data_ra',
+    'cpu_stq_be_data_ra',
+    'cpu_stw_le_data_ra',
+    'cpu_stl_le_data_ra',
+    'cpu_stq_le_data_ra',
     'cpu_loop_exit',
     'cpu_loop_exit_atomic',
     'cpu_loop_exit_noexc',

qemu/include/exec/cpu_ldst.h

@@ -87,42 +87,6 @@ typedef target_ulong abi_ptr;
 #define TARGET_ABI_FMT_ptr TARGET_ABI_FMT_lx
 #endif
 
-#if defined(CONFIG_USER_ONLY)
-
-/* In user-only mode we provide only the _code and _data accessors. */
-
-#define MEMSUFFIX _data
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_useronly_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_useronly_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_useronly_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_useronly_template.h"
-#undef MEMSUFFIX
-
-#define MEMSUFFIX _code
-#define CODE_ACCESS
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_useronly_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_useronly_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_useronly_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_useronly_template.h"
-#undef MEMSUFFIX
-#undef CODE_ACCESS
-
-#else
-
 /* The memory helpers for tcg-generated code need tcg_target_long etc.  */
 #include "tcg.h"
 
@@ -149,277 +113,159 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
     return &env->tlb_table[mmu_idx][tlb_index(env, mmu_idx, addr)];
 }
 
-#ifdef MMU_MODE0_SUFFIX
+uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
-#define CPU_MMU_INDEX 0
+                            int mmu_idx, uintptr_t ra);
-#define MEMSUFFIX MMU_MODE0_SUFFIX
+int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
-#define DATA_SIZE 1
+                       int mmu_idx, uintptr_t ra);
-#include "exec/cpu_ldst_template.h"
+
-
+uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
-#define DATA_SIZE 2
+                               int mmu_idx, uintptr_t ra);
-#include "exec/cpu_ldst_template.h"
+int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
-
+                          int mmu_idx, uintptr_t ra);
-#define DATA_SIZE 4
+uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
-#include "exec/cpu_ldst_template.h"
+                              int mmu_idx, uintptr_t ra);
-
+uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
-#define DATA_SIZE 8
+                              int mmu_idx, uintptr_t ra);
-#include "exec/cpu_ldst_template.h"
+
-#undef CPU_MMU_INDEX
+uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
-#undef MEMSUFFIX
+                               int mmu_idx, uintptr_t ra);
-#endif
+int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
-
+                          int mmu_idx, uintptr_t ra);
-#if (NB_MMU_MODES >= 2) && defined(MMU_MODE1_SUFFIX)
+uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
-#define CPU_MMU_INDEX 1
+                              int mmu_idx, uintptr_t ra);
-#define MEMSUFFIX MMU_MODE1_SUFFIX
+uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
-#define DATA_SIZE 1
+                              int mmu_idx, uintptr_t ra);
-#include "exec/cpu_ldst_template.h"
+
-
+void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif
-
-#if (NB_MMU_MODES >= 3) && defined(MMU_MODE2_SUFFIX)
-
-#define CPU_MMU_INDEX 2
-#define MEMSUFFIX MMU_MODE2_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 3) */
-
-#if (NB_MMU_MODES >= 4) && defined(MMU_MODE3_SUFFIX)
-
-#define CPU_MMU_INDEX 3
-#define MEMSUFFIX MMU_MODE3_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 4) */
-
-#if (NB_MMU_MODES >= 5) && defined(MMU_MODE4_SUFFIX)
-
-#define CPU_MMU_INDEX 4
-#define MEMSUFFIX MMU_MODE4_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 5) */
-
-#if (NB_MMU_MODES >= 6) && defined(MMU_MODE5_SUFFIX)
-
-#define CPU_MMU_INDEX 5
-#define MEMSUFFIX MMU_MODE5_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 6) */
-
-#if (NB_MMU_MODES >= 7) && defined(MMU_MODE6_SUFFIX)
-
-#define CPU_MMU_INDEX 6
-#define MEMSUFFIX MMU_MODE6_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 7) */
-
-#if (NB_MMU_MODES >= 8) && defined(MMU_MODE7_SUFFIX)
-
-#define CPU_MMU_INDEX 7
-#define MEMSUFFIX MMU_MODE7_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 8) */
-
-#if (NB_MMU_MODES >= 9) && defined(MMU_MODE8_SUFFIX)
-
-#define CPU_MMU_INDEX 8
-#define MEMSUFFIX MMU_MODE8_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 9) */
-
-#if (NB_MMU_MODES >= 10) && defined(MMU_MODE9_SUFFIX)
-
-#define CPU_MMU_INDEX 9
-#define MEMSUFFIX MMU_MODE9_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 10) */
-
-#if (NB_MMU_MODES >= 11) && defined(MMU_MODE10_SUFFIX)
-
-#define CPU_MMU_INDEX 10
-#define MEMSUFFIX MMU_MODE10_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 11) */
-
-#if (NB_MMU_MODES >= 12) && defined(MMU_MODE11_SUFFIX)
-
-#define CPU_MMU_INDEX 11
-#define MEMSUFFIX MMU_MODE11_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 12) */
-
-#if (NB_MMU_MODES > 12)
-#error "NB_MMU_MODES > 12 is not supported for now"
-#endif /* (NB_MMU_MODES > 12) */
-
-/* these access are slower, they must be as rare as possible */
-#define CPU_MMU_INDEX (cpu_mmu_index(env, false))
-#define MEMSUFFIX _data
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-
-#define CPU_MMU_INDEX (cpu_mmu_index(env, true))
-#define MEMSUFFIX _code
-#define SOFTMMU_CODE_ACCESS
-
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#undef SOFTMMU_CODE_ACCESS
-
-void cpu_stb_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
                        int mmu_idx, uintptr_t retaddr);
 
-#endif /* defined(CONFIG_USER_ONLY) */
+void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
+                          int mmu_idx, uintptr_t retaddr);
+void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
+                          int mmu_idx, uintptr_t retaddr);
+void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
+                          int mmu_idx, uintptr_t retaddr);
+
+void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
+                          int mmu_idx, uintptr_t retaddr);
+void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
+                          int mmu_idx, uintptr_t retaddr);
+void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
+                          int mmu_idx, uintptr_t retaddr);
+
+uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
+int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr);
+
+uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr);
+int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr);
+uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr);
+uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr);
+
+uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr);
+int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr);
+uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr);
+uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr);
+
+uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
+int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
+
+uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
+int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
+uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
+uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
+
+uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
+int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
+uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
+uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
+
+void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
+
+void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
+void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
+void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
+
+void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
+void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
+void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
+
+void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
+                     uint32_t val, uintptr_t ra);
+
+void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
+                        uint32_t val, uintptr_t ra);
+void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
+                        uint32_t val, uintptr_t ra);
+void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
+                        uint64_t val, uintptr_t ra);
+
+void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
+                        uint32_t val, uintptr_t ra);
+void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
+                        uint32_t val, uintptr_t ra);
+void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
+                        uint64_t val, uintptr_t ra);
+
+#ifdef TARGET_WORDS_BIGENDIAN
+# define cpu_lduw_data        cpu_lduw_be_data
+# define cpu_ldsw_data        cpu_ldsw_be_data
+# define cpu_ldl_data         cpu_ldl_be_data
+# define cpu_ldq_data         cpu_ldq_be_data
+# define cpu_lduw_data_ra     cpu_lduw_be_data_ra
+# define cpu_ldsw_data_ra     cpu_ldsw_be_data_ra
+# define cpu_ldl_data_ra      cpu_ldl_be_data_ra
+# define cpu_ldq_data_ra      cpu_ldq_be_data_ra
+# define cpu_lduw_mmuidx_ra   cpu_lduw_be_mmuidx_ra
+# define cpu_ldsw_mmuidx_ra   cpu_ldsw_be_mmuidx_ra
+# define cpu_ldl_mmuidx_ra    cpu_ldl_be_mmuidx_ra
+# define cpu_ldq_mmuidx_ra    cpu_ldq_be_mmuidx_ra
+# define cpu_stw_data         cpu_stw_be_data
+# define cpu_stl_data         cpu_stl_be_data
+# define cpu_stq_data         cpu_stq_be_data
+# define cpu_stw_data_ra      cpu_stw_be_data_ra
+# define cpu_stl_data_ra      cpu_stl_be_data_ra
+# define cpu_stq_data_ra      cpu_stq_be_data_ra
+# define cpu_stw_mmuidx_ra    cpu_stw_be_mmuidx_ra
+# define cpu_stl_mmuidx_ra    cpu_stl_be_mmuidx_ra
+# define cpu_stq_mmuidx_ra    cpu_stq_be_mmuidx_ra
+#else
+# define cpu_lduw_data        cpu_lduw_le_data
+# define cpu_ldsw_data        cpu_ldsw_le_data
+# define cpu_ldl_data         cpu_ldl_le_data
+# define cpu_ldq_data         cpu_ldq_le_data
+# define cpu_lduw_data_ra     cpu_lduw_le_data_ra
+# define cpu_ldsw_data_ra     cpu_ldsw_le_data_ra
+# define cpu_ldl_data_ra      cpu_ldl_le_data_ra
+# define cpu_ldq_data_ra      cpu_ldq_le_data_ra
+# define cpu_lduw_mmuidx_ra   cpu_lduw_le_mmuidx_ra
+# define cpu_ldsw_mmuidx_ra   cpu_ldsw_le_mmuidx_ra
+# define cpu_ldl_mmuidx_ra    cpu_ldl_le_mmuidx_ra
+# define cpu_ldq_mmuidx_ra    cpu_ldq_le_mmuidx_ra
+# define cpu_stw_data         cpu_stw_le_data
+# define cpu_stl_data         cpu_stl_le_data
+# define cpu_stq_data         cpu_stq_le_data
+# define cpu_stw_data_ra      cpu_stw_le_data_ra
+# define cpu_stl_data_ra      cpu_stl_le_data_ra
+# define cpu_stq_data_ra      cpu_stq_le_data_ra
+# define cpu_stw_mmuidx_ra    cpu_stw_le_mmuidx_ra
+# define cpu_stl_mmuidx_ra    cpu_stl_le_mmuidx_ra
+# define cpu_stq_mmuidx_ra    cpu_stq_le_mmuidx_ra
+#endif
+
+uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
+uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr);
+uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr);
+uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr);
+
+static inline int cpu_ldsb_code(CPUArchState *env, abi_ptr addr)
+{
+    return (int8_t)cpu_ldub_code(env, addr);
+}
+
+static inline int cpu_ldsw_code(CPUArchState *env, abi_ptr addr)
+{
+    return (int16_t)cpu_lduw_code(env, addr);
+}
 
 /**
  * tlb_vaddr_to_host:

qemu/m68k.h

@@ -303,6 +303,61 @@
 #define cpu_ldl_code cpu_ldl_code_m68k
 #define cpu_ldub_code cpu_ldub_code_m68k
 #define cpu_lduw_code cpu_lduw_code_m68k
+#define cpu_ldub_code cpu_ldub_code_m68k
+#define cpu_lduw_code cpu_lduw_code_m68k
+#define cpu_ldl_code cpu_ldl_code_m68k
+#define cpu_ldq_code cpu_ldq_code_m68k
+#define cpu_ldub_mmuidx_ra cpu_ldub_mmuidx_ra_m68k
+#define cpu_ldsb_mmuidx_ra cpu_ldsb_mmuidx_ra_m68k
+#define cpu_lduw_be_mmuidx_ra cpu_lduw_be_mmuidx_ra_m68k
+#define cpu_ldsw_be_mmuidx_ra cpu_ldsw_be_mmuidx_ra_m68k
+#define cpu_ldl_be_mmuidx_ra cpu_ldl_be_mmuidx_ra_m68k
+#define cpu_ldq_be_mmuidx_ra cpu_ldq_be_mmuidx_ra_m68k
+#define cpu_lduw_le_mmuidx_ra cpu_lduw_le_mmuidx_ra_m68k
+#define cpu_ldsw_le_mmuidx_ra cpu_ldsw_le_mmuidx_ra_m68k
+#define cpu_ldl_le_mmuidx_ra cpu_ldl_le_mmuidx_ra_m68k
+#define cpu_ldq_le_mmuidx_ra cpu_ldq_le_mmuidx_ra_m68k
+#define cpu_stb_mmuidx_ra cpu_stb_mmuidx_ra_m68k
+#define cpu_stw_be_mmuidx_ra cpu_stw_be_mmuidx_ra_m68k
+#define cpu_stl_be_mmuidx_ra cpu_stl_be_mmuidx_ra_m68k
+#define cpu_stq_be_mmuidx_ra cpu_stq_be_mmuidx_ra_m68k
+#define cpu_stw_le_mmuidx_ra cpu_stw_le_mmuidx_ra_m68k
+#define cpu_stl_le_mmuidx_ra cpu_stl_le_mmuidx_ra_m68k
+#define cpu_stq_le_mmuidx_ra cpu_stq_le_mmuidx_ra_m68k
+#define cpu_ldub_data cpu_ldub_data_m68k
+#define cpu_ldsb_data cpu_ldsb_data_m68k
+#define cpu_lduw_be_data cpu_lduw_be_data_m68k
+#define cpu_ldsw_be_data cpu_ldsw_be_data_m68k
+#define cpu_ldl_be_data cpu_ldl_be_data_m68k
+#define cpu_ldq_be_data cpu_ldq_be_data_m68k
+#define cpu_lduw_le_data cpu_lduw_le_data_m68k
+#define cpu_ldsw_le_data cpu_ldsw_le_data_m68k
+#define cpu_ldl_le_data cpu_ldl_le_data_m68k
+#define cpu_ldq_le_data cpu_ldq_le_data_m68k
+#define cpu_ldub_data_ra cpu_ldub_data_ra_m68k
+#define cpu_ldsb_data_ra cpu_ldsb_data_ra_m68k
+#define cpu_lduw_be_data_ra cpu_lduw_be_data_ra_m68k
+#define cpu_ldsw_be_data_ra cpu_ldsw_be_data_ra_m68k
+#define cpu_ldl_be_data_ra cpu_ldl_be_data_ra_m68k
+#define cpu_ldq_be_data_ra cpu_ldq_be_data_ra_m68k
+#define cpu_lduw_le_data_ra cpu_lduw_le_data_ra_m68k
+#define cpu_ldsw_le_data_ra cpu_ldsw_le_data_ra_m68k
+#define cpu_ldl_le_data_ra cpu_ldl_le_data_ra_m68k
+#define cpu_ldq_le_data_ra cpu_ldq_le_data_ra_m68k
+#define cpu_stb_data cpu_stb_data_m68k
+#define cpu_stw_be_data cpu_stw_be_data_m68k
+#define cpu_stl_be_data cpu_stl_be_data_m68k
+#define cpu_stq_be_data cpu_stq_be_data_m68k
+#define cpu_stw_le_data cpu_stw_le_data_m68k
+#define cpu_stl_le_data cpu_stl_le_data_m68k
+#define cpu_stq_le_data cpu_stq_le_data_m68k
+#define cpu_stb_data_ra cpu_stb_data_ra_m68k
+#define cpu_stw_be_data_ra cpu_stw_be_data_ra_m68k
+#define cpu_stl_be_data_ra cpu_stl_be_data_ra_m68k
+#define cpu_stq_be_data_ra cpu_stq_be_data_ra_m68k
+#define cpu_stw_le_data_ra cpu_stw_le_data_ra_m68k
+#define cpu_stl_le_data_ra cpu_stl_le_data_ra_m68k
+#define cpu_stq_le_data_ra cpu_stq_le_data_ra_m68k
 #define cpu_loop_exit cpu_loop_exit_m68k
 #define cpu_loop_exit_atomic cpu_loop_exit_atomic_m68k
 #define cpu_loop_exit_noexc cpu_loop_exit_noexc_m68k

qemu/mips.h

@@ -303,6 +303,61 @@
 #define cpu_ldl_code cpu_ldl_code_mips
 #define cpu_ldub_code cpu_ldub_code_mips
 #define cpu_lduw_code cpu_lduw_code_mips
+#define cpu_ldub_code cpu_ldub_code_mips
+#define cpu_lduw_code cpu_lduw_code_mips
+#define cpu_ldl_code cpu_ldl_code_mips
+#define cpu_ldq_code cpu_ldq_code_mips
+#define cpu_ldub_mmuidx_ra cpu_ldub_mmuidx_ra_mips
+#define cpu_ldsb_mmuidx_ra cpu_ldsb_mmuidx_ra_mips
+#define cpu_lduw_be_mmuidx_ra cpu_lduw_be_mmuidx_ra_mips
+#define cpu_ldsw_be_mmuidx_ra cpu_ldsw_be_mmuidx_ra_mips
+#define cpu_ldl_be_mmuidx_ra cpu_ldl_be_mmuidx_ra_mips
+#define cpu_ldq_be_mmuidx_ra cpu_ldq_be_mmuidx_ra_mips
+#define cpu_lduw_le_mmuidx_ra cpu_lduw_le_mmuidx_ra_mips
+#define cpu_ldsw_le_mmuidx_ra cpu_ldsw_le_mmuidx_ra_mips
+#define cpu_ldl_le_mmuidx_ra cpu_ldl_le_mmuidx_ra_mips
+#define cpu_ldq_le_mmuidx_ra cpu_ldq_le_mmuidx_ra_mips
+#define cpu_stb_mmuidx_ra cpu_stb_mmuidx_ra_mips
+#define cpu_stw_be_mmuidx_ra cpu_stw_be_mmuidx_ra_mips
+#define cpu_stl_be_mmuidx_ra cpu_stl_be_mmuidx_ra_mips
+#define cpu_stq_be_mmuidx_ra cpu_stq_be_mmuidx_ra_mips
+#define cpu_stw_le_mmuidx_ra cpu_stw_le_mmuidx_ra_mips
+#define cpu_stl_le_mmuidx_ra cpu_stl_le_mmuidx_ra_mips
+#define cpu_stq_le_mmuidx_ra cpu_stq_le_mmuidx_ra_mips
+#define cpu_ldub_data cpu_ldub_data_mips
+#define cpu_ldsb_data cpu_ldsb_data_mips
+#define cpu_lduw_be_data cpu_lduw_be_data_mips
+#define cpu_ldsw_be_data cpu_ldsw_be_data_mips
+#define cpu_ldl_be_data cpu_ldl_be_data_mips
+#define cpu_ldq_be_data cpu_ldq_be_data_mips
+#define cpu_lduw_le_data cpu_lduw_le_data_mips
+#define cpu_ldsw_le_data cpu_ldsw_le_data_mips
+#define cpu_ldl_le_data cpu_ldl_le_data_mips
+#define cpu_ldq_le_data cpu_ldq_le_data_mips
+#define cpu_ldub_data_ra cpu_ldub_data_ra_mips
+#define cpu_ldsb_data_ra cpu_ldsb_data_ra_mips
+#define cpu_lduw_be_data_ra cpu_lduw_be_data_ra_mips
+#define cpu_ldsw_be_data_ra cpu_ldsw_be_data_ra_mips
+#define cpu_ldl_be_data_ra cpu_ldl_be_data_ra_mips
+#define cpu_ldq_be_data_ra cpu_ldq_be_data_ra_mips
+#define cpu_lduw_le_data_ra cpu_lduw_le_data_ra_mips
+#define cpu_ldsw_le_data_ra cpu_ldsw_le_data_ra_mips
+#define cpu_ldl_le_data_ra cpu_ldl_le_data_ra_mips
+#define cpu_ldq_le_data_ra cpu_ldq_le_data_ra_mips
+#define cpu_stb_data cpu_stb_data_mips
+#define cpu_stw_be_data cpu_stw_be_data_mips
+#define cpu_stl_be_data cpu_stl_be_data_mips
+#define cpu_stq_be_data cpu_stq_be_data_mips
+#define cpu_stw_le_data cpu_stw_le_data_mips
+#define cpu_stl_le_data cpu_stl_le_data_mips
+#define cpu_stq_le_data cpu_stq_le_data_mips
+#define cpu_stb_data_ra cpu_stb_data_ra_mips
+#define cpu_stw_be_data_ra cpu_stw_be_data_ra_mips
+#define cpu_stl_be_data_ra cpu_stl_be_data_ra_mips
+#define cpu_stq_be_data_ra cpu_stq_be_data_ra_mips
+#define cpu_stw_le_data_ra cpu_stw_le_data_ra_mips
+#define cpu_stl_le_data_ra cpu_stl_le_data_ra_mips
+#define cpu_stq_le_data_ra cpu_stq_le_data_ra_mips
 #define cpu_loop_exit cpu_loop_exit_mips
 #define cpu_loop_exit_atomic cpu_loop_exit_atomic_mips
 #define cpu_loop_exit_noexc cpu_loop_exit_noexc_mips

qemu/mips64.h

@@ -303,6 +303,61 @@
 #define cpu_ldl_code cpu_ldl_code_mips64
 #define cpu_ldub_code cpu_ldub_code_mips64
 #define cpu_lduw_code cpu_lduw_code_mips64
+#define cpu_ldub_code cpu_ldub_code_mips64
+#define cpu_lduw_code cpu_lduw_code_mips64
+#define cpu_ldl_code cpu_ldl_code_mips64
+#define cpu_ldq_code cpu_ldq_code_mips64
+#define cpu_ldub_mmuidx_ra cpu_ldub_mmuidx_ra_mips64
+#define cpu_ldsb_mmuidx_ra cpu_ldsb_mmuidx_ra_mips64
+#define cpu_lduw_be_mmuidx_ra cpu_lduw_be_mmuidx_ra_mips64
+#define cpu_ldsw_be_mmuidx_ra cpu_ldsw_be_mmuidx_ra_mips64
+#define cpu_ldl_be_mmuidx_ra cpu_ldl_be_mmuidx_ra_mips64
+#define cpu_ldq_be_mmuidx_ra cpu_ldq_be_mmuidx_ra_mips64
+#define cpu_lduw_le_mmuidx_ra cpu_lduw_le_mmuidx_ra_mips64
+#define cpu_ldsw_le_mmuidx_ra cpu_ldsw_le_mmuidx_ra_mips64
+#define cpu_ldl_le_mmuidx_ra cpu_ldl_le_mmuidx_ra_mips64
+#define cpu_ldq_le_mmuidx_ra cpu_ldq_le_mmuidx_ra_mips64
+#define cpu_stb_mmuidx_ra cpu_stb_mmuidx_ra_mips64
+#define cpu_stw_be_mmuidx_ra cpu_stw_be_mmuidx_ra_mips64
+#define cpu_stl_be_mmuidx_ra cpu_stl_be_mmuidx_ra_mips64
+#define cpu_stq_be_mmuidx_ra cpu_stq_be_mmuidx_ra_mips64
+#define cpu_stw_le_mmuidx_ra cpu_stw_le_mmuidx_ra_mips64
+#define cpu_stl_le_mmuidx_ra cpu_stl_le_mmuidx_ra_mips64
+#define cpu_stq_le_mmuidx_ra cpu_stq_le_mmuidx_ra_mips64
+#define cpu_ldub_data cpu_ldub_data_mips64
+#define cpu_ldsb_data cpu_ldsb_data_mips64
+#define cpu_lduw_be_data cpu_lduw_be_data_mips64
+#define cpu_ldsw_be_data cpu_ldsw_be_data_mips64
+#define cpu_ldl_be_data cpu_ldl_be_data_mips64
+#define cpu_ldq_be_data cpu_ldq_be_data_mips64
+#define cpu_lduw_le_data cpu_lduw_le_data_mips64
+#define cpu_ldsw_le_data cpu_ldsw_le_data_mips64
+#define cpu_ldl_le_data cpu_ldl_le_data_mips64
+#define cpu_ldq_le_data cpu_ldq_le_data_mips64
+#define cpu_ldub_data_ra cpu_ldub_data_ra_mips64
+#define cpu_ldsb_data_ra cpu_ldsb_data_ra_mips64
+#define cpu_lduw_be_data_ra cpu_lduw_be_data_ra_mips64
+#define cpu_ldsw_be_data_ra cpu_ldsw_be_data_ra_mips64
+#define cpu_ldl_be_data_ra cpu_ldl_be_data_ra_mips64
+#define cpu_ldq_be_data_ra cpu_ldq_be_data_ra_mips64
+#define cpu_lduw_le_data_ra cpu_lduw_le_data_ra_mips64
+#define cpu_ldsw_le_data_ra cpu_ldsw_le_data_ra_mips64
+#define cpu_ldl_le_data_ra cpu_ldl_le_data_ra_mips64
+#define cpu_ldq_le_data_ra cpu_ldq_le_data_ra_mips64
+#define cpu_stb_data cpu_stb_data_mips64
+#define cpu_stw_be_data cpu_stw_be_data_mips64
+#define cpu_stl_be_data cpu_stl_be_data_mips64
+#define cpu_stq_be_data cpu_stq_be_data_mips64
+#define cpu_stw_le_data cpu_stw_le_data_mips64
+#define cpu_stl_le_data cpu_stl_le_data_mips64
+#define cpu_stq_le_data cpu_stq_le_data_mips64
+#define cpu_stb_data_ra cpu_stb_data_ra_mips64
+#define cpu_stw_be_data_ra cpu_stw_be_data_ra_mips64
+#define cpu_stl_be_data_ra cpu_stl_be_data_ra_mips64
+#define cpu_stq_be_data_ra cpu_stq_be_data_ra_mips64
+#define cpu_stw_le_data_ra cpu_stw_le_data_ra_mips64
+#define cpu_stl_le_data_ra cpu_stl_le_data_ra_mips64
+#define cpu_stq_le_data_ra cpu_stq_le_data_ra_mips64
 #define cpu_loop_exit cpu_loop_exit_mips64
 #define cpu_loop_exit_atomic cpu_loop_exit_atomic_mips64
 #define cpu_loop_exit_noexc cpu_loop_exit_noexc_mips64

qemu/mips64el.h

@@ -303,6 +303,61 @@
 #define cpu_ldl_code cpu_ldl_code_mips64el
 #define cpu_ldub_code cpu_ldub_code_mips64el
 #define cpu_lduw_code cpu_lduw_code_mips64el
+#define cpu_ldub_code cpu_ldub_code_mips64el
+#define cpu_lduw_code cpu_lduw_code_mips64el
+#define cpu_ldl_code cpu_ldl_code_mips64el
+#define cpu_ldq_code cpu_ldq_code_mips64el
+#define cpu_ldub_mmuidx_ra cpu_ldub_mmuidx_ra_mips64el
+#define cpu_ldsb_mmuidx_ra cpu_ldsb_mmuidx_ra_mips64el
+#define cpu_lduw_be_mmuidx_ra cpu_lduw_be_mmuidx_ra_mips64el
+#define cpu_ldsw_be_mmuidx_ra cpu_ldsw_be_mmuidx_ra_mips64el
+#define cpu_ldl_be_mmuidx_ra cpu_ldl_be_mmuidx_ra_mips64el
+#define cpu_ldq_be_mmuidx_ra cpu_ldq_be_mmuidx_ra_mips64el
+#define cpu_lduw_le_mmuidx_ra cpu_lduw_le_mmuidx_ra_mips64el
+#define cpu_ldsw_le_mmuidx_ra cpu_ldsw_le_mmuidx_ra_mips64el
+#define cpu_ldl_le_mmuidx_ra cpu_ldl_le_mmuidx_ra_mips64el
+#define cpu_ldq_le_mmuidx_ra cpu_ldq_le_mmuidx_ra_mips64el
+#define cpu_stb_mmuidx_ra cpu_stb_mmuidx_ra_mips64el
+#define cpu_stw_be_mmuidx_ra cpu_stw_be_mmuidx_ra_mips64el
+#define cpu_stl_be_mmuidx_ra cpu_stl_be_mmuidx_ra_mips64el
+#define cpu_stq_be_mmuidx_ra cpu_stq_be_mmuidx_ra_mips64el
+#define cpu_stw_le_mmuidx_ra cpu_stw_le_mmuidx_ra_mips64el
+#define cpu_stl_le_mmuidx_ra cpu_stl_le_mmuidx_ra_mips64el
+#define cpu_stq_le_mmuidx_ra cpu_stq_le_mmuidx_ra_mips64el
+#define cpu_ldub_data cpu_ldub_data_mips64el
+#define cpu_ldsb_data cpu_ldsb_data_mips64el
+#define cpu_lduw_be_data cpu_lduw_be_data_mips64el
+#define cpu_ldsw_be_data cpu_ldsw_be_data_mips64el
+#define cpu_ldl_be_data cpu_ldl_be_data_mips64el
+#define cpu_ldq_be_data cpu_ldq_be_data_mips64el
+#define cpu_lduw_le_data cpu_lduw_le_data_mips64el
+#define cpu_ldsw_le_data cpu_ldsw_le_data_mips64el
+#define cpu_ldl_le_data cpu_ldl_le_data_mips64el
+#define cpu_ldq_le_data cpu_ldq_le_data_mips64el
+#define cpu_ldub_data_ra cpu_ldub_data_ra_mips64el
+#define cpu_ldsb_data_ra cpu_ldsb_data_ra_mips64el
+#define cpu_lduw_be_data_ra cpu_lduw_be_data_ra_mips64el
+#define cpu_ldsw_be_data_ra cpu_ldsw_be_data_ra_mips64el
+#define cpu_ldl_be_data_ra cpu_ldl_be_data_ra_mips64el
+#define cpu_ldq_be_data_ra cpu_ldq_be_data_ra_mips64el
+#define cpu_lduw_le_data_ra cpu_lduw_le_data_ra_mips64el
+#define cpu_ldsw_le_data_ra cpu_ldsw_le_data_ra_mips64el
+#define cpu_ldl_le_data_ra cpu_ldl_le_data_ra_mips64el
+#define cpu_ldq_le_data_ra cpu_ldq_le_data_ra_mips64el
+#define cpu_stb_data cpu_stb_data_mips64el
+#define cpu_stw_be_data cpu_stw_be_data_mips64el
+#define cpu_stl_be_data cpu_stl_be_data_mips64el
+#define cpu_stq_be_data cpu_stq_be_data_mips64el
+#define cpu_stw_le_data cpu_stw_le_data_mips64el
+#define cpu_stl_le_data cpu_stl_le_data_mips64el
+#define cpu_stq_le_data cpu_stq_le_data_mips64el
+#define cpu_stb_data_ra cpu_stb_data_ra_mips64el
+#define cpu_stw_be_data_ra cpu_stw_be_data_ra_mips64el
+#define cpu_stl_be_data_ra cpu_stl_be_data_ra_mips64el
+#define cpu_stq_be_data_ra cpu_stq_be_data_ra_mips64el
+#define cpu_stw_le_data_ra cpu_stw_le_data_ra_mips64el
+#define cpu_stl_le_data_ra cpu_stl_le_data_ra_mips64el
+#define cpu_stq_le_data_ra cpu_stq_le_data_ra_mips64el
 #define cpu_loop_exit cpu_loop_exit_mips64el
 #define cpu_loop_exit_atomic cpu_loop_exit_atomic_mips64el
 #define cpu_loop_exit_noexc cpu_loop_exit_noexc_mips64el

qemu/mipsel.h

@@ -303,6 +303,61 @@
 #define cpu_ldl_code cpu_ldl_code_mipsel
 #define cpu_ldub_code cpu_ldub_code_mipsel
 #define cpu_lduw_code cpu_lduw_code_mipsel
+#define cpu_ldub_code cpu_ldub_code_mipsel
+#define cpu_lduw_code cpu_lduw_code_mipsel
+#define cpu_ldl_code cpu_ldl_code_mipsel
+#define cpu_ldq_code cpu_ldq_code_mipsel
+#define cpu_ldub_mmuidx_ra cpu_ldub_mmuidx_ra_mipsel
+#define cpu_ldsb_mmuidx_ra cpu_ldsb_mmuidx_ra_mipsel
+#define cpu_lduw_be_mmuidx_ra cpu_lduw_be_mmuidx_ra_mipsel
+#define cpu_ldsw_be_mmuidx_ra cpu_ldsw_be_mmuidx_ra_mipsel
+#define cpu_ldl_be_mmuidx_ra cpu_ldl_be_mmuidx_ra_mipsel
+#define cpu_ldq_be_mmuidx_ra cpu_ldq_be_mmuidx_ra_mipsel
+#define cpu_lduw_le_mmuidx_ra cpu_lduw_le_mmuidx_ra_mipsel
+#define cpu_ldsw_le_mmuidx_ra cpu_ldsw_le_mmuidx_ra_mipsel
+#define cpu_ldl_le_mmuidx_ra cpu_ldl_le_mmuidx_ra_mipsel
+#define cpu_ldq_le_mmuidx_ra cpu_ldq_le_mmuidx_ra_mipsel
+#define cpu_stb_mmuidx_ra cpu_stb_mmuidx_ra_mipsel
+#define cpu_stw_be_mmuidx_ra cpu_stw_be_mmuidx_ra_mipsel
+#define cpu_stl_be_mmuidx_ra cpu_stl_be_mmuidx_ra_mipsel
+#define cpu_stq_be_mmuidx_ra cpu_stq_be_mmuidx_ra_mipsel
+#define cpu_stw_le_mmuidx_ra cpu_stw_le_mmuidx_ra_mipsel
+#define cpu_stl_le_mmuidx_ra cpu_stl_le_mmuidx_ra_mipsel
+#define cpu_stq_le_mmuidx_ra cpu_stq_le_mmuidx_ra_mipsel
+#define cpu_ldub_data cpu_ldub_data_mipsel
+#define cpu_ldsb_data cpu_ldsb_data_mipsel
+#define cpu_lduw_be_data cpu_lduw_be_data_mipsel
+#define cpu_ldsw_be_data cpu_ldsw_be_data_mipsel
+#define cpu_ldl_be_data cpu_ldl_be_data_mipsel
+#define cpu_ldq_be_data cpu_ldq_be_data_mipsel
+#define cpu_lduw_le_data cpu_lduw_le_data_mipsel
+#define cpu_ldsw_le_data cpu_ldsw_le_data_mipsel
+#define cpu_ldl_le_data cpu_ldl_le_data_mipsel
+#define cpu_ldq_le_data cpu_ldq_le_data_mipsel
+#define cpu_ldub_data_ra cpu_ldub_data_ra_mipsel
+#define cpu_ldsb_data_ra cpu_ldsb_data_ra_mipsel
+#define cpu_lduw_be_data_ra cpu_lduw_be_data_ra_mipsel
+#define cpu_ldsw_be_data_ra cpu_ldsw_be_data_ra_mipsel
+#define cpu_ldl_be_data_ra cpu_ldl_be_data_ra_mipsel
+#define cpu_ldq_be_data_ra cpu_ldq_be_data_ra_mipsel
+#define cpu_lduw_le_data_ra cpu_lduw_le_data_ra_mipsel
+#define cpu_ldsw_le_data_ra cpu_ldsw_le_data_ra_mipsel
+#define cpu_ldl_le_data_ra cpu_ldl_le_data_ra_mipsel
+#define cpu_ldq_le_data_ra cpu_ldq_le_data_ra_mipsel
+#define cpu_stb_data cpu_stb_data_mipsel
+#define cpu_stw_be_data cpu_stw_be_data_mipsel
+#define cpu_stl_be_data cpu_stl_be_data_mipsel
+#define cpu_stq_be_data cpu_stq_be_data_mipsel
+#define cpu_stw_le_data cpu_stw_le_data_mipsel
+#define cpu_stl_le_data cpu_stl_le_data_mipsel
+#define cpu_stq_le_data cpu_stq_le_data_mipsel
+#define cpu_stb_data_ra cpu_stb_data_ra_mipsel
+#define cpu_stw_be_data_ra cpu_stw_be_data_ra_mipsel
+#define cpu_stl_be_data_ra cpu_stl_be_data_ra_mipsel
+#define cpu_stq_be_data_ra cpu_stq_be_data_ra_mipsel
+#define cpu_stw_le_data_ra cpu_stw_le_data_ra_mipsel
+#define cpu_stl_le_data_ra cpu_stl_le_data_ra_mipsel
+#define cpu_stq_le_data_ra cpu_stq_le_data_ra_mipsel
 #define cpu_loop_exit cpu_loop_exit_mipsel
 #define cpu_loop_exit_atomic cpu_loop_exit_atomic_mipsel
 #define cpu_loop_exit_noexc cpu_loop_exit_noexc_mipsel

qemu/powerpc.h

@@ -303,6 +303,61 @@
 #define cpu_ldl_code cpu_ldl_code_powerpc
 #define cpu_ldub_code cpu_ldub_code_powerpc
 #define cpu_lduw_code cpu_lduw_code_powerpc
+#define cpu_ldub_code cpu_ldub_code_powerpc
+#define cpu_lduw_code cpu_lduw_code_powerpc
+#define cpu_ldl_code cpu_ldl_code_powerpc
+#define cpu_ldq_code cpu_ldq_code_powerpc
+#define cpu_ldub_mmuidx_ra cpu_ldub_mmuidx_ra_powerpc
+#define cpu_ldsb_mmuidx_ra cpu_ldsb_mmuidx_ra_powerpc
+#define cpu_lduw_be_mmuidx_ra cpu_lduw_be_mmuidx_ra_powerpc
+#define cpu_ldsw_be_mmuidx_ra cpu_ldsw_be_mmuidx_ra_powerpc
+#define cpu_ldl_be_mmuidx_ra cpu_ldl_be_mmuidx_ra_powerpc
+#define cpu_ldq_be_mmuidx_ra cpu_ldq_be_mmuidx_ra_powerpc
+#define cpu_lduw_le_mmuidx_ra cpu_lduw_le_mmuidx_ra_powerpc
+#define cpu_ldsw_le_mmuidx_ra cpu_ldsw_le_mmuidx_ra_powerpc
+#define cpu_ldl_le_mmuidx_ra cpu_ldl_le_mmuidx_ra_powerpc
+#define cpu_ldq_le_mmuidx_ra cpu_ldq_le_mmuidx_ra_powerpc
+#define cpu_stb_mmuidx_ra cpu_stb_mmuidx_ra_powerpc
+#define cpu_stw_be_mmuidx_ra cpu_stw_be_mmuidx_ra_powerpc
+#define cpu_stl_be_mmuidx_ra cpu_stl_be_mmuidx_ra_powerpc
+#define cpu_stq_be_mmuidx_ra cpu_stq_be_mmuidx_ra_powerpc
+#define cpu_stw_le_mmuidx_ra cpu_stw_le_mmuidx_ra_powerpc
+#define cpu_stl_le_mmuidx_ra cpu_stl_le_mmuidx_ra_powerpc
+#define cpu_stq_le_mmuidx_ra cpu_stq_le_mmuidx_ra_powerpc
+#define cpu_ldub_data cpu_ldub_data_powerpc
+#define cpu_ldsb_data cpu_ldsb_data_powerpc
+#define cpu_lduw_be_data cpu_lduw_be_data_powerpc
+#define cpu_ldsw_be_data cpu_ldsw_be_data_powerpc
+#define cpu_ldl_be_data cpu_ldl_be_data_powerpc
+#define cpu_ldq_be_data cpu_ldq_be_data_powerpc
+#define cpu_lduw_le_data cpu_lduw_le_data_powerpc
+#define cpu_ldsw_le_data cpu_ldsw_le_data_powerpc
+#define cpu_ldl_le_data cpu_ldl_le_data_powerpc
+#define cpu_ldq_le_data cpu_ldq_le_data_powerpc
+#define cpu_ldub_data_ra cpu_ldub_data_ra_powerpc
+#define cpu_ldsb_data_ra cpu_ldsb_data_ra_powerpc
+#define cpu_lduw_be_data_ra cpu_lduw_be_data_ra_powerpc
+#define cpu_ldsw_be_data_ra cpu_ldsw_be_data_ra_powerpc
+#define cpu_ldl_be_data_ra cpu_ldl_be_data_ra_powerpc
+#define cpu_ldq_be_data_ra cpu_ldq_be_data_ra_powerpc
+#define cpu_lduw_le_data_ra cpu_lduw_le_data_ra_powerpc
+#define cpu_ldsw_le_data_ra cpu_ldsw_le_data_ra_powerpc
+#define cpu_ldl_le_data_ra cpu_ldl_le_data_ra_powerpc
+#define cpu_ldq_le_data_ra cpu_ldq_le_data_ra_powerpc
+#define cpu_stb_data cpu_stb_data_powerpc
+#define cpu_stw_be_data cpu_stw_be_data_powerpc
+#define cpu_stl_be_data cpu_stl_be_data_powerpc
+#define cpu_stq_be_data cpu_stq_be_data_powerpc
+#define cpu_stw_le_data cpu_stw_le_data_powerpc
+#define cpu_stl_le_data cpu_stl_le_data_powerpc
+#define cpu_stq_le_data cpu_stq_le_data_powerpc
+#define cpu_stb_data_ra cpu_stb_data_ra_powerpc
+#define cpu_stw_be_data_ra cpu_stw_be_data_ra_powerpc
+#define cpu_stl_be_data_ra cpu_stl_be_data_ra_powerpc
+#define cpu_stq_be_data_ra cpu_stq_be_data_ra_powerpc
+#define cpu_stw_le_data_ra cpu_stw_le_data_ra_powerpc
+#define cpu_stl_le_data_ra cpu_stl_le_data_ra_powerpc
+#define cpu_stq_le_data_ra cpu_stq_le_data_ra_powerpc
 #define cpu_loop_exit cpu_loop_exit_powerpc
 #define cpu_loop_exit_atomic cpu_loop_exit_atomic_powerpc
 #define cpu_loop_exit_noexc cpu_loop_exit_noexc_powerpc

qemu/riscv32.h

@@ -303,6 +303,61 @@
 #define cpu_ldl_code cpu_ldl_code_riscv32
 #define cpu_ldub_code cpu_ldub_code_riscv32
 #define cpu_lduw_code cpu_lduw_code_riscv32
+#define cpu_ldub_code cpu_ldub_code_riscv32
+#define cpu_lduw_code cpu_lduw_code_riscv32
+#define cpu_ldl_code cpu_ldl_code_riscv32
+#define cpu_ldq_code cpu_ldq_code_riscv32
+#define cpu_ldub_mmuidx_ra cpu_ldub_mmuidx_ra_riscv32
+#define cpu_ldsb_mmuidx_ra cpu_ldsb_mmuidx_ra_riscv32
+#define cpu_lduw_be_mmuidx_ra cpu_lduw_be_mmuidx_ra_riscv32
+#define cpu_ldsw_be_mmuidx_ra cpu_ldsw_be_mmuidx_ra_riscv32
+#define cpu_ldl_be_mmuidx_ra cpu_ldl_be_mmuidx_ra_riscv32
+#define cpu_ldq_be_mmuidx_ra cpu_ldq_be_mmuidx_ra_riscv32
+#define cpu_lduw_le_mmuidx_ra cpu_lduw_le_mmuidx_ra_riscv32
+#define cpu_ldsw_le_mmuidx_ra cpu_ldsw_le_mmuidx_ra_riscv32
+#define cpu_ldl_le_mmuidx_ra cpu_ldl_le_mmuidx_ra_riscv32
+#define cpu_ldq_le_mmuidx_ra cpu_ldq_le_mmuidx_ra_riscv32
+#define cpu_stb_mmuidx_ra cpu_stb_mmuidx_ra_riscv32
+#define cpu_stw_be_mmuidx_ra cpu_stw_be_mmuidx_ra_riscv32
+#define cpu_stl_be_mmuidx_ra cpu_stl_be_mmuidx_ra_riscv32
+#define cpu_stq_be_mmuidx_ra cpu_stq_be_mmuidx_ra_riscv32
+#define cpu_stw_le_mmuidx_ra cpu_stw_le_mmuidx_ra_riscv32
+#define cpu_stl_le_mmuidx_ra cpu_stl_le_mmuidx_ra_riscv32
+#define cpu_stq_le_mmuidx_ra cpu_stq_le_mmuidx_ra_riscv32
+#define cpu_ldub_data cpu_ldub_data_riscv32
+#define cpu_ldsb_data cpu_ldsb_data_riscv32
+#define cpu_lduw_be_data cpu_lduw_be_data_riscv32
+#define cpu_ldsw_be_data cpu_ldsw_be_data_riscv32
+#define cpu_ldl_be_data cpu_ldl_be_data_riscv32
+#define cpu_ldq_be_data cpu_ldq_be_data_riscv32
+#define cpu_lduw_le_data cpu_lduw_le_data_riscv32
+#define cpu_ldsw_le_data cpu_ldsw_le_data_riscv32
+#define cpu_ldl_le_data cpu_ldl_le_data_riscv32
+#define cpu_ldq_le_data cpu_ldq_le_data_riscv32
+#define cpu_ldub_data_ra cpu_ldub_data_ra_riscv32
+#define cpu_ldsb_data_ra cpu_ldsb_data_ra_riscv32
+#define cpu_lduw_be_data_ra cpu_lduw_be_data_ra_riscv32
+#define cpu_ldsw_be_data_ra cpu_ldsw_be_data_ra_riscv32
+#define cpu_ldl_be_data_ra cpu_ldl_be_data_ra_riscv32
+#define cpu_ldq_be_data_ra cpu_ldq_be_data_ra_riscv32
+#define cpu_lduw_le_data_ra cpu_lduw_le_data_ra_riscv32
+#define cpu_ldsw_le_data_ra cpu_ldsw_le_data_ra_riscv32
+#define cpu_ldl_le_data_ra cpu_ldl_le_data_ra_riscv32
+#define cpu_ldq_le_data_ra cpu_ldq_le_data_ra_riscv32
+#define cpu_stb_data cpu_stb_data_riscv32
+#define cpu_stw_be_data cpu_stw_be_data_riscv32
+#define cpu_stl_be_data cpu_stl_be_data_riscv32
+#define cpu_stq_be_data cpu_stq_be_data_riscv32
+#define cpu_stw_le_data cpu_stw_le_data_riscv32
+#define cpu_stl_le_data cpu_stl_le_data_riscv32
+#define cpu_stq_le_data cpu_stq_le_data_riscv32
+#define cpu_stb_data_ra cpu_stb_data_ra_riscv32
+#define cpu_stw_be_data_ra cpu_stw_be_data_ra_riscv32
+#define cpu_stl_be_data_ra cpu_stl_be_data_ra_riscv32
+#define cpu_stq_be_data_ra cpu_stq_be_data_ra_riscv32
+#define cpu_stw_le_data_ra cpu_stw_le_data_ra_riscv32
+#define cpu_stl_le_data_ra cpu_stl_le_data_ra_riscv32
+#define cpu_stq_le_data_ra cpu_stq_le_data_ra_riscv32
 #define cpu_loop_exit cpu_loop_exit_riscv32
 #define cpu_loop_exit_atomic cpu_loop_exit_atomic_riscv32
 #define cpu_loop_exit_noexc cpu_loop_exit_noexc_riscv32

qemu/riscv64.h

@@ -303,6 +303,61 @@
 #define cpu_ldl_code cpu_ldl_code_riscv64
 #define cpu_ldub_code cpu_ldub_code_riscv64
 #define cpu_lduw_code cpu_lduw_code_riscv64
+#define cpu_ldub_code cpu_ldub_code_riscv64
+#define cpu_lduw_code cpu_lduw_code_riscv64
+#define cpu_ldl_code cpu_ldl_code_riscv64
+#define cpu_ldq_code cpu_ldq_code_riscv64
+#define cpu_ldub_mmuidx_ra cpu_ldub_mmuidx_ra_riscv64
+#define cpu_ldsb_mmuidx_ra cpu_ldsb_mmuidx_ra_riscv64
+#define cpu_lduw_be_mmuidx_ra cpu_lduw_be_mmuidx_ra_riscv64
+#define cpu_ldsw_be_mmuidx_ra cpu_ldsw_be_mmuidx_ra_riscv64
+#define cpu_ldl_be_mmuidx_ra cpu_ldl_be_mmuidx_ra_riscv64
+#define cpu_ldq_be_mmuidx_ra cpu_ldq_be_mmuidx_ra_riscv64
+#define cpu_lduw_le_mmuidx_ra cpu_lduw_le_mmuidx_ra_riscv64
+#define cpu_ldsw_le_mmuidx_ra cpu_ldsw_le_mmuidx_ra_riscv64
+#define cpu_ldl_le_mmuidx_ra cpu_ldl_le_mmuidx_ra_riscv64
+#define cpu_ldq_le_mmuidx_ra cpu_ldq_le_mmuidx_ra_riscv64
+#define cpu_stb_mmuidx_ra cpu_stb_mmuidx_ra_riscv64
+#define cpu_stw_be_mmuidx_ra cpu_stw_be_mmuidx_ra_riscv64
+#define cpu_stl_be_mmuidx_ra cpu_stl_be_mmuidx_ra_riscv64
+#define cpu_stq_be_mmuidx_ra cpu_stq_be_mmuidx_ra_riscv64
+#define cpu_stw_le_mmuidx_ra cpu_stw_le_mmuidx_ra_riscv64
+#define cpu_stl_le_mmuidx_ra cpu_stl_le_mmuidx_ra_riscv64
+#define cpu_stq_le_mmuidx_ra cpu_stq_le_mmuidx_ra_riscv64
+#define cpu_ldub_data cpu_ldub_data_riscv64
+#define cpu_ldsb_data cpu_ldsb_data_riscv64
+#define cpu_lduw_be_data cpu_lduw_be_data_riscv64
+#define cpu_ldsw_be_data cpu_ldsw_be_data_riscv64
+#define cpu_ldl_be_data cpu_ldl_be_data_riscv64
+#define cpu_ldq_be_data cpu_ldq_be_data_riscv64
+#define cpu_lduw_le_data cpu_lduw_le_data_riscv64
+#define cpu_ldsw_le_data cpu_ldsw_le_data_riscv64
+#define cpu_ldl_le_data cpu_ldl_le_data_riscv64
+#define cpu_ldq_le_data cpu_ldq_le_data_riscv64
+#define cpu_ldub_data_ra cpu_ldub_data_ra_riscv64
+#define cpu_ldsb_data_ra cpu_ldsb_data_ra_riscv64
+#define cpu_lduw_be_data_ra cpu_lduw_be_data_ra_riscv64
+#define cpu_ldsw_be_data_ra cpu_ldsw_be_data_ra_riscv64
+#define cpu_ldl_be_data_ra cpu_ldl_be_data_ra_riscv64
+#define cpu_ldq_be_data_ra cpu_ldq_be_data_ra_riscv64
+#define cpu_lduw_le_data_ra cpu_lduw_le_data_ra_riscv64
+#define cpu_ldsw_le_data_ra cpu_ldsw_le_data_ra_riscv64
+#define cpu_ldl_le_data_ra cpu_ldl_le_data_ra_riscv64
+#define cpu_ldq_le_data_ra cpu_ldq_le_data_ra_riscv64
+#define cpu_stb_data cpu_stb_data_riscv64
+#define cpu_stw_be_data cpu_stw_be_data_riscv64
+#define cpu_stl_be_data cpu_stl_be_data_riscv64
+#define cpu_stq_be_data cpu_stq_be_data_riscv64
+#define cpu_stw_le_data cpu_stw_le_data_riscv64
+#define cpu_stl_le_data cpu_stl_le_data_riscv64
+#define cpu_stq_le_data cpu_stq_le_data_riscv64
+#define cpu_stb_data_ra cpu_stb_data_ra_riscv64
+#define cpu_stw_be_data_ra cpu_stw_be_data_ra_riscv64
+#define cpu_stl_be_data_ra cpu_stl_be_data_ra_riscv64
+#define cpu_stq_be_data_ra cpu_stq_be_data_ra_riscv64
+#define cpu_stw_le_data_ra cpu_stw_le_data_ra_riscv64
+#define cpu_stl_le_data_ra cpu_stl_le_data_ra_riscv64
+#define cpu_stq_le_data_ra cpu_stq_le_data_ra_riscv64
 #define cpu_loop_exit cpu_loop_exit_riscv64
 #define cpu_loop_exit_atomic cpu_loop_exit_atomic_riscv64
 #define cpu_loop_exit_noexc cpu_loop_exit_noexc_riscv64

qemu/sparc.h

@@ -303,6 +303,61 @@
 #define cpu_ldl_code cpu_ldl_code_sparc
 #define cpu_ldub_code cpu_ldub_code_sparc
 #define cpu_lduw_code cpu_lduw_code_sparc
+#define cpu_ldub_code cpu_ldub_code_sparc
+#define cpu_lduw_code cpu_lduw_code_sparc
+#define cpu_ldl_code cpu_ldl_code_sparc
+#define cpu_ldq_code cpu_ldq_code_sparc
+#define cpu_ldub_mmuidx_ra cpu_ldub_mmuidx_ra_sparc
+#define cpu_ldsb_mmuidx_ra cpu_ldsb_mmuidx_ra_sparc
+#define cpu_lduw_be_mmuidx_ra cpu_lduw_be_mmuidx_ra_sparc
+#define cpu_ldsw_be_mmuidx_ra cpu_ldsw_be_mmuidx_ra_sparc
+#define cpu_ldl_be_mmuidx_ra cpu_ldl_be_mmuidx_ra_sparc
+#define cpu_ldq_be_mmuidx_ra cpu_ldq_be_mmuidx_ra_sparc
+#define cpu_lduw_le_mmuidx_ra cpu_lduw_le_mmuidx_ra_sparc
+#define cpu_ldsw_le_mmuidx_ra cpu_ldsw_le_mmuidx_ra_sparc
+#define cpu_ldl_le_mmuidx_ra cpu_ldl_le_mmuidx_ra_sparc
+#define cpu_ldq_le_mmuidx_ra cpu_ldq_le_mmuidx_ra_sparc
+#define cpu_stb_mmuidx_ra cpu_stb_mmuidx_ra_sparc
+#define cpu_stw_be_mmuidx_ra cpu_stw_be_mmuidx_ra_sparc
+#define cpu_stl_be_mmuidx_ra cpu_stl_be_mmuidx_ra_sparc
+#define cpu_stq_be_mmuidx_ra cpu_stq_be_mmuidx_ra_sparc
+#define cpu_stw_le_mmuidx_ra cpu_stw_le_mmuidx_ra_sparc
+#define cpu_stl_le_mmuidx_ra cpu_stl_le_mmuidx_ra_sparc
+#define cpu_stq_le_mmuidx_ra cpu_stq_le_mmuidx_ra_sparc
+#define cpu_ldub_data cpu_ldub_data_sparc
+#define cpu_ldsb_data cpu_ldsb_data_sparc
+#define cpu_lduw_be_data cpu_lduw_be_data_sparc
+#define cpu_ldsw_be_data cpu_ldsw_be_data_sparc
+#define cpu_ldl_be_data cpu_ldl_be_data_sparc
+#define cpu_ldq_be_data cpu_ldq_be_data_sparc
+#define cpu_lduw_le_data cpu_lduw_le_data_sparc
+#define cpu_ldsw_le_data cpu_ldsw_le_data_sparc
+#define cpu_ldl_le_data cpu_ldl_le_data_sparc
+#define cpu_ldq_le_data cpu_ldq_le_data_sparc
+#define cpu_ldub_data_ra cpu_ldub_data_ra_sparc
+#define cpu_ldsb_data_ra cpu_ldsb_data_ra_sparc
+#define cpu_lduw_be_data_ra cpu_lduw_be_data_ra_sparc
+#define cpu_ldsw_be_data_ra cpu_ldsw_be_data_ra_sparc
+#define cpu_ldl_be_data_ra cpu_ldl_be_data_ra_sparc
+#define cpu_ldq_be_data_ra cpu_ldq_be_data_ra_sparc
+#define cpu_lduw_le_data_ra cpu_lduw_le_data_ra_sparc
+#define cpu_ldsw_le_data_ra cpu_ldsw_le_data_ra_sparc
+#define cpu_ldl_le_data_ra cpu_ldl_le_data_ra_sparc
+#define cpu_ldq_le_data_ra cpu_ldq_le_data_ra_sparc
+#define cpu_stb_data cpu_stb_data_sparc
+#define cpu_stw_be_data cpu_stw_be_data_sparc
+#define cpu_stl_be_data cpu_stl_be_data_sparc
+#define cpu_stq_be_data cpu_stq_be_data_sparc
+#define cpu_stw_le_data cpu_stw_le_data_sparc
+#define cpu_stl_le_data cpu_stl_le_data_sparc
+#define cpu_stq_le_data cpu_stq_le_data_sparc
+#define cpu_stb_data_ra cpu_stb_data_ra_sparc
+#define cpu_stw_be_data_ra cpu_stw_be_data_ra_sparc
+#define cpu_stl_be_data_ra cpu_stl_be_data_ra_sparc
+#define cpu_stq_be_data_ra cpu_stq_be_data_ra_sparc
+#define cpu_stw_le_data_ra cpu_stw_le_data_ra_sparc
+#define cpu_stl_le_data_ra cpu_stl_le_data_ra_sparc
+#define cpu_stq_le_data_ra cpu_stq_le_data_ra_sparc
 #define cpu_loop_exit cpu_loop_exit_sparc
 #define cpu_loop_exit_atomic cpu_loop_exit_atomic_sparc
 #define cpu_loop_exit_noexc cpu_loop_exit_noexc_sparc

qemu/sparc64.h

@@ -303,6 +303,61 @@
 #define cpu_ldl_code cpu_ldl_code_sparc64
 #define cpu_ldub_code cpu_ldub_code_sparc64
 #define cpu_lduw_code cpu_lduw_code_sparc64
+#define cpu_ldub_code cpu_ldub_code_sparc64
+#define cpu_lduw_code cpu_lduw_code_sparc64
+#define cpu_ldl_code cpu_ldl_code_sparc64
+#define cpu_ldq_code cpu_ldq_code_sparc64
+#define cpu_ldub_mmuidx_ra cpu_ldub_mmuidx_ra_sparc64
+#define cpu_ldsb_mmuidx_ra cpu_ldsb_mmuidx_ra_sparc64
+#define cpu_lduw_be_mmuidx_ra cpu_lduw_be_mmuidx_ra_sparc64
+#define cpu_ldsw_be_mmuidx_ra cpu_ldsw_be_mmuidx_ra_sparc64
+#define cpu_ldl_be_mmuidx_ra cpu_ldl_be_mmuidx_ra_sparc64
+#define cpu_ldq_be_mmuidx_ra cpu_ldq_be_mmuidx_ra_sparc64
+#define cpu_lduw_le_mmuidx_ra cpu_lduw_le_mmuidx_ra_sparc64
+#define cpu_ldsw_le_mmuidx_ra cpu_ldsw_le_mmuidx_ra_sparc64
+#define cpu_ldl_le_mmuidx_ra cpu_ldl_le_mmuidx_ra_sparc64
+#define cpu_ldq_le_mmuidx_ra cpu_ldq_le_mmuidx_ra_sparc64
+#define cpu_stb_mmuidx_ra cpu_stb_mmuidx_ra_sparc64
+#define cpu_stw_be_mmuidx_ra cpu_stw_be_mmuidx_ra_sparc64
+#define cpu_stl_be_mmuidx_ra cpu_stl_be_mmuidx_ra_sparc64
+#define cpu_stq_be_mmuidx_ra cpu_stq_be_mmuidx_ra_sparc64
+#define cpu_stw_le_mmuidx_ra cpu_stw_le_mmuidx_ra_sparc64
+#define cpu_stl_le_mmuidx_ra cpu_stl_le_mmuidx_ra_sparc64
+#define cpu_stq_le_mmuidx_ra cpu_stq_le_mmuidx_ra_sparc64
+#define cpu_ldub_data cpu_ldub_data_sparc64
+#define cpu_ldsb_data cpu_ldsb_data_sparc64
+#define cpu_lduw_be_data cpu_lduw_be_data_sparc64
+#define cpu_ldsw_be_data cpu_ldsw_be_data_sparc64
+#define cpu_ldl_be_data cpu_ldl_be_data_sparc64
+#define cpu_ldq_be_data cpu_ldq_be_data_sparc64
+#define cpu_lduw_le_data cpu_lduw_le_data_sparc64
+#define cpu_ldsw_le_data cpu_ldsw_le_data_sparc64
+#define cpu_ldl_le_data cpu_ldl_le_data_sparc64
+#define cpu_ldq_le_data cpu_ldq_le_data_sparc64
+#define cpu_ldub_data_ra cpu_ldub_data_ra_sparc64
+#define cpu_ldsb_data_ra cpu_ldsb_data_ra_sparc64
+#define cpu_lduw_be_data_ra cpu_lduw_be_data_ra_sparc64
+#define cpu_ldsw_be_data_ra cpu_ldsw_be_data_ra_sparc64
+#define cpu_ldl_be_data_ra cpu_ldl_be_data_ra_sparc64
+#define cpu_ldq_be_data_ra cpu_ldq_be_data_ra_sparc64
+#define cpu_lduw_le_data_ra cpu_lduw_le_data_ra_sparc64
+#define cpu_ldsw_le_data_ra cpu_ldsw_le_data_ra_sparc64
+#define cpu_ldl_le_data_ra cpu_ldl_le_data_ra_sparc64
+#define cpu_ldq_le_data_ra cpu_ldq_le_data_ra_sparc64
+#define cpu_stb_data cpu_stb_data_sparc64
+#define cpu_stw_be_data cpu_stw_be_data_sparc64
+#define cpu_stl_be_data cpu_stl_be_data_sparc64
+#define cpu_stq_be_data cpu_stq_be_data_sparc64
+#define cpu_stw_le_data cpu_stw_le_data_sparc64
+#define cpu_stl_le_data cpu_stl_le_data_sparc64
+#define cpu_stq_le_data cpu_stq_le_data_sparc64
+#define cpu_stb_data_ra cpu_stb_data_ra_sparc64
+#define cpu_stw_be_data_ra cpu_stw_be_data_ra_sparc64
+#define cpu_stl_be_data_ra cpu_stl_be_data_ra_sparc64
+#define cpu_stq_be_data_ra cpu_stq_be_data_ra_sparc64
+#define cpu_stw_le_data_ra cpu_stw_le_data_ra_sparc64
+#define cpu_stl_le_data_ra cpu_stl_le_data_ra_sparc64
+#define cpu_stq_le_data_ra cpu_stq_le_data_ra_sparc64
 #define cpu_loop_exit cpu_loop_exit_sparc64
 #define cpu_loop_exit_atomic cpu_loop_exit_atomic_sparc64
 #define cpu_loop_exit_noexc cpu_loop_exit_noexc_sparc64

qemu/target/arm/sve_helper.c

@@ -3953,9 +3953,8 @@ typedef intptr_t sve_ld1_host_fn(void *vd, void *vg, void *host,
  * Load one element into @vd + @reg_off from (@env, @vaddr, @ra).
  * The controlling predicate is known to be true.
  */
-typedef void sve_ld1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off,
+typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off,
-                            target_ulong vaddr, TCGMemOpIdx oi, uintptr_t ra);
+                              target_ulong vaddr, uintptr_t retaddr);
-typedef sve_ld1_tlb_fn sve_st1_tlb_fn;
 
 /*
  * Generate the above primitives.
@@ -3978,27 +3977,23 @@ static intptr_t sve_##NAME##_host(void *vd, void *vg, void *host,           \
     return mem_off;                                                         \
 }
 
-#ifdef CONFIG_SOFTMMU
+#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \
-#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, HOST, MOEND, TLB) \
 static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off,  \
-                             target_ulong addr, TCGMemOpIdx oi, uintptr_t ra)  \
+                             target_ulong addr, uintptr_t ra)               \
 {                                                                           \
-    TYPEM val = TLB(env, addr, oi, ra);                                     \
+    *(TYPEE *)(vd + H(reg_off)) = (TYPEM)TLB(env, addr, ra);                \
-    *(TYPEE *)(vd + H(reg_off)) = val;                                      \
 }
-#else
+
-#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, HOST, MOEND, TLB)                  \
+#define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) \
 static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off,  \
-                             target_ulong addr, TCGMemOpIdx oi, uintptr_t ra)  \
+                             target_ulong addr, uintptr_t ra)               \
 {                                                                           \
-    TYPEM val = HOST(g2h(addr));                                            \
+    TLB(env, addr, (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra);                 \
-    *(TYPEE *)(vd + H(reg_off)) = val;                                      \
 }
-#endif
 
 #define DO_LD_PRIM_1(NAME, H, TE, TM)                   \
     DO_LD_HOST(NAME, H, TE, TM, ldub_p)                 \
-    DO_LD_TLB(NAME, H, TE, TM, ldub_p, 0, helper_ret_ldub_mmu)
+    DO_LD_TLB(NAME, H, TE, TM, cpu_ldub_data_ra)
 
 DO_LD_PRIM_1(ld1bb,  H1,   uint8_t,  uint8_t)
 DO_LD_PRIM_1(ld1bhu, H1_2, uint16_t, uint8_t)
@@ -4008,39 +4003,51 @@ DO_LD_PRIM_1(ld1bss, H1_4, uint32_t,  int8_t)
 DO_LD_PRIM_1(ld1bdu,     , uint64_t, uint8_t)
 DO_LD_PRIM_1(ld1bds,     , uint64_t,  int8_t)
 
-#define DO_LD_PRIM_2(NAME, end, MOEND, H, TE, TM, PH, PT)  \
+#define DO_ST_PRIM_1(NAME, H, TE, TM)                   \
-    DO_LD_HOST(NAME##_##end, H, TE, TM, PH##_##end##_p)    \
+    DO_ST_TLB(st1##NAME, H, TE, TM, cpu_stb_data_ra)
-    DO_LD_TLB(NAME##_##end, H, TE, TM, PH##_##end##_p,     \
-              MOEND, helper_##end##_##PT##_mmu)
 
-DO_LD_PRIM_2(ld1hh,  le, MO_LE, H1_2, uint16_t, uint16_t, lduw, lduw)
+DO_ST_PRIM_1(bb,   H1,  uint8_t, uint8_t)
-DO_LD_PRIM_2(ld1hsu, le, MO_LE, H1_4, uint32_t, uint16_t, lduw, lduw)
+DO_ST_PRIM_1(bh, H1_2, uint16_t, uint8_t)
-DO_LD_PRIM_2(ld1hss, le, MO_LE, H1_4, uint32_t,  int16_t, lduw, lduw)
+DO_ST_PRIM_1(bs, H1_4, uint32_t, uint8_t)
-DO_LD_PRIM_2(ld1hdu, le, MO_LE,     , uint64_t, uint16_t, lduw, lduw)
+DO_ST_PRIM_1(bd,     , uint64_t, uint8_t)
-DO_LD_PRIM_2(ld1hds, le, MO_LE,     , uint64_t,  int16_t, lduw, lduw)
 
-DO_LD_PRIM_2(ld1ss,  le, MO_LE, H1_4, uint32_t, uint32_t, ldl, ldul)
+#define DO_LD_PRIM_2(NAME, H, TE, TM, LD) \
-DO_LD_PRIM_2(ld1sdu, le, MO_LE,     , uint64_t, uint32_t, ldl, ldul)
+    DO_LD_HOST(ld1##NAME##_be, H, TE, TM, LD##_be_p)    \
-DO_LD_PRIM_2(ld1sds, le, MO_LE,     , uint64_t,  int32_t, ldl, ldul)
+    DO_LD_HOST(ld1##NAME##_le, H, TE, TM, LD##_le_p)    \
+    DO_LD_TLB(ld1##NAME##_be, H, TE, TM, cpu_##LD##_be_data_ra) \
+    DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra)
 
-DO_LD_PRIM_2(ld1dd,  le, MO_LE,     , uint64_t, uint64_t, ldq, ldq)
+#define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \
+    DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \
+    DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra)
 
-DO_LD_PRIM_2(ld1hh,  be, MO_BE, H1_2, uint16_t, uint16_t, lduw, lduw)
+DO_LD_PRIM_2(hh,  H1_2, uint16_t, uint16_t, lduw)
-DO_LD_PRIM_2(ld1hsu, be, MO_BE, H1_4, uint32_t, uint16_t, lduw, lduw)
+DO_LD_PRIM_2(hsu, H1_4, uint32_t, uint16_t, lduw)
-DO_LD_PRIM_2(ld1hss, be, MO_BE, H1_4, uint32_t,  int16_t, lduw, lduw)
+DO_LD_PRIM_2(hss, H1_4, uint32_t,  int16_t, lduw)
-DO_LD_PRIM_2(ld1hdu, be, MO_BE,     , uint64_t, uint16_t, lduw, lduw)
+DO_LD_PRIM_2(hdu,     , uint64_t, uint16_t, lduw)
-DO_LD_PRIM_2(ld1hds, be, MO_BE,     , uint64_t,  int16_t, lduw, lduw)
+DO_LD_PRIM_2(hds,     , uint64_t,  int16_t, lduw)
 
-DO_LD_PRIM_2(ld1ss,  be, MO_BE, H1_4, uint32_t, uint32_t, ldl, ldul)
+DO_ST_PRIM_2(hh, H1_2, uint16_t, uint16_t, stw)
-DO_LD_PRIM_2(ld1sdu, be, MO_BE,     , uint64_t, uint32_t, ldl, ldul)
+DO_ST_PRIM_2(hs, H1_4, uint32_t, uint16_t, stw)
-DO_LD_PRIM_2(ld1sds, be, MO_BE,     , uint64_t,  int32_t, ldl, ldul)
+DO_ST_PRIM_2(hd,     , uint64_t, uint16_t, stw)
 
-DO_LD_PRIM_2(ld1dd,  be, MO_BE,     , uint64_t, uint64_t, ldq, ldq)
+DO_LD_PRIM_2(ss,  H1_4, uint32_t, uint32_t, ldl)
+DO_LD_PRIM_2(sdu,     , uint64_t, uint32_t, ldl)
+DO_LD_PRIM_2(sds,     , uint64_t,  int32_t, ldl)
+
+DO_ST_PRIM_2(ss, H1_4, uint32_t, uint32_t, stl)
+DO_ST_PRIM_2(sd,     , uint64_t, uint32_t, stl)
+
+DO_LD_PRIM_2(dd,     , uint64_t, uint64_t, ldq)
+DO_ST_PRIM_2(dd,     , uint64_t, uint64_t, stq)
 
 #undef DO_LD_TLB
+#undef DO_ST_TLB
 #undef DO_LD_HOST
 #undef DO_LD_PRIM_1
+#undef DO_ST_PRIM_1
 #undef DO_LD_PRIM_2
+#undef DO_ST_PRIM_2
 
 /*
  * Skip through a sequence of inactive elements in the guarding predicate @vg,
@@ -4115,7 +4122,7 @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
                       uint32_t desc, const uintptr_t retaddr,
                       const int esz, const int msz,
                       sve_ld1_host_fn *host_fn,
-                      sve_ld1_tlb_fn *tlb_fn)
+                      sve_ldst1_tlb_fn *tlb_fn)
 {
     const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
     const int mmu_idx = get_mmuidx(oi);
@@ -4197,7 +4204,7 @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr,
          * on I/O memory, it may succeed but not bring in the TLB entry.
          * But even then we have still made forward progress.
          */
-        tlb_fn(env, &scratch, reg_off, addr + mem_off, oi, retaddr);
+        tlb_fn(env, &scratch, reg_off, addr + mem_off, retaddr);
         reg_off += 1 << esz;
     }
 #endif
@@ -4256,9 +4263,8 @@ DO_LD1_2(ld1dd,  3, 3)
  */
 static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
                       uint32_t desc, int size, uintptr_t ra,
-                      sve_ld1_tlb_fn *tlb_fn)
+                      sve_ldst1_tlb_fn *tlb_fn)
 {
-    const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
     const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
     intptr_t i, oprsz = simd_oprsz(desc);
     ARMVectorReg scratch[2] = { };
@@ -4268,8 +4274,8 @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
         uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
         do {
             if (pg & 1) {
-                tlb_fn(env, &scratch[0], i, addr, oi, ra);
+                tlb_fn(env, &scratch[0], i, addr, ra);
-                tlb_fn(env, &scratch[1], i, addr + size, oi, ra);
+                tlb_fn(env, &scratch[1], i, addr + size, ra);
             }
             i += size, pg >>= size;
             addr += 2 * size;
@@ -4284,9 +4290,8 @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr,
 
 static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
                       uint32_t desc, int size, uintptr_t ra,
-                      sve_ld1_tlb_fn *tlb_fn)
+                      sve_ldst1_tlb_fn *tlb_fn)
 {
-    const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
     const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
     intptr_t i, oprsz = simd_oprsz(desc);
     ARMVectorReg scratch[3] = { };
@@ -4296,9 +4301,9 @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
         uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
         do {
             if (pg & 1) {
-                tlb_fn(env, &scratch[0], i, addr, oi, ra);
+                tlb_fn(env, &scratch[0], i, addr, ra);
-                tlb_fn(env, &scratch[1], i, addr + size, oi, ra);
+                tlb_fn(env, &scratch[1], i, addr + size, ra);
-                tlb_fn(env, &scratch[2], i, addr + 2 * size, oi, ra);
+                tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
             }
             i += size, pg >>= size;
             addr += 3 * size;
@@ -4314,9 +4319,8 @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr,
 
 static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
                       uint32_t desc, int size, uintptr_t ra,
-                      sve_ld1_tlb_fn *tlb_fn)
+                      sve_ldst1_tlb_fn *tlb_fn)
 {
-    const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
     const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
     intptr_t i, oprsz = simd_oprsz(desc);
     ARMVectorReg scratch[4] = { };
@@ -4326,10 +4330,10 @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr,
         uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
         do {
             if (pg & 1) {
-                tlb_fn(env, &scratch[0], i, addr, oi, ra);
+                tlb_fn(env, &scratch[0], i, addr, ra);
-                tlb_fn(env, &scratch[1], i, addr + size, oi, ra);
+                tlb_fn(env, &scratch[1], i, addr + size, ra);
-                tlb_fn(env, &scratch[2], i, addr + 2 * size, oi, ra);
+                tlb_fn(env, &scratch[2], i, addr + 2 * size, ra);
-                tlb_fn(env, &scratch[3], i, addr + 3 * size, oi, ra);
+                tlb_fn(env, &scratch[3], i, addr + 3 * size, ra);
             }
             i += size, pg >>= size;
             addr += 4 * size;
@@ -4422,7 +4426,7 @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
                         uint32_t desc, const uintptr_t retaddr,
                         const int esz, const int msz,
                         sve_ld1_host_fn *host_fn,
-                        sve_ld1_tlb_fn *tlb_fn)
+                        sve_ldst1_tlb_fn *tlb_fn)
 {
     const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
     const int mmu_idx = get_mmuidx(oi);
@@ -4482,7 +4486,7 @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr,
      * Perform one normal read, which will fault or not.
      * But it is likely to bring the page into the tlb.
      */
-    tlb_fn(env, vd, reg_off, addr + mem_off, oi, retaddr);
+    tlb_fn(env, vd, reg_off, addr + mem_off, retaddr);
 
     /* After any fault, zero any leading predicated false elts.  */
     swap_memzero(vd, reg_off);
@@ -4635,60 +4639,14 @@ DO_LDFF1_LDNF1_2(dd,  3, 3)
 #undef DO_LDFF1_LDNF1_1
 #undef DO_LDFF1_LDNF1_2
 
-/*
- * Store contiguous data, protected by a governing predicate.
- */
-
-#ifdef CONFIG_SOFTMMU
-#define DO_ST_TLB(NAME, H, TYPEM, HOST, MOEND, TLB) \
-static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off,  \
-                             target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
-{                                                                           \
-    TLB(env, addr, *(TYPEM *)(vd + H(reg_off)), oi, ra);                    \
-}
-#else
-#define DO_ST_TLB(NAME, H, TYPEM, HOST, MOEND, TLB) \
-static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off,  \
-                             target_ulong addr, TCGMemOpIdx oi, uintptr_t ra) \
-{                                                                           \
-    HOST(g2h(addr), *(TYPEM *)(vd + H(reg_off)));                           \
-}
-#endif
-
-DO_ST_TLB(st1bb,   H1,  uint8_t, stb_p, 0, helper_ret_stb_mmu)
-DO_ST_TLB(st1bh, H1_2, uint16_t, stb_p, 0, helper_ret_stb_mmu)
-DO_ST_TLB(st1bs, H1_4, uint32_t, stb_p, 0, helper_ret_stb_mmu)
-DO_ST_TLB(st1bd,     , uint64_t, stb_p, 0, helper_ret_stb_mmu)
-
-DO_ST_TLB(st1hh_le, H1_2, uint16_t, stw_le_p, MO_LE, helper_le_stw_mmu)
-DO_ST_TLB(st1hs_le, H1_4, uint32_t, stw_le_p, MO_LE, helper_le_stw_mmu)
-DO_ST_TLB(st1hd_le,     , uint64_t, stw_le_p, MO_LE, helper_le_stw_mmu)
-
-DO_ST_TLB(st1ss_le, H1_4, uint32_t, stl_le_p, MO_LE, helper_le_stl_mmu)
-DO_ST_TLB(st1sd_le,     , uint64_t, stl_le_p, MO_LE, helper_le_stl_mmu)
-
-DO_ST_TLB(st1dd_le,     , uint64_t, stq_le_p, MO_LE, helper_le_stq_mmu)
-
-DO_ST_TLB(st1hh_be, H1_2, uint16_t, stw_be_p, MO_BE, helper_be_stw_mmu)
-DO_ST_TLB(st1hs_be, H1_4, uint32_t, stw_be_p, MO_BE, helper_be_stw_mmu)
-DO_ST_TLB(st1hd_be,     , uint64_t, stw_be_p, MO_BE, helper_be_stw_mmu)
-
-DO_ST_TLB(st1ss_be, H1_4, uint32_t, stl_be_p, MO_BE, helper_be_stl_mmu)
-DO_ST_TLB(st1sd_be,     , uint64_t, stl_be_p, MO_BE, helper_be_stl_mmu)
-
-DO_ST_TLB(st1dd_be,     , uint64_t, stq_be_p, MO_BE, helper_be_stq_mmu)
-
-#undef DO_ST_TLB
-
 /*
  * Common helpers for all contiguous 1,2,3,4-register predicated stores.
  */
 static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
                       uint32_t desc, const uintptr_t ra,
                       const int esize, const int msize,
-                      sve_st1_tlb_fn *tlb_fn)
+                      sve_ldst1_tlb_fn *tlb_fn)
 {
-    const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
     const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
     intptr_t i, oprsz = simd_oprsz(desc);
     void *vd = &env->vfp.zregs[rd];
@@ -4698,7 +4656,7 @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
         uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
         do {
             if (pg & 1) {
-                tlb_fn(env, vd, i, addr, oi, ra);
+                tlb_fn(env, vd, i, addr, ra);
             }
             i += esize, pg >>= esize;
             addr += msize;
@@ -4710,9 +4668,8 @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr,
 static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
                       uint32_t desc, const uintptr_t ra,
                       const int esize, const int msize,
-                      sve_st1_tlb_fn *tlb_fn)
+                      sve_ldst1_tlb_fn *tlb_fn)
 {
-    const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
     const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
     intptr_t i, oprsz = simd_oprsz(desc);
     void *d1 = &env->vfp.zregs[rd];
@@ -4723,8 +4680,8 @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
         uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
         do {
             if (pg & 1) {
-                tlb_fn(env, d1, i, addr, oi, ra);
+                tlb_fn(env, d1, i, addr, ra);
-                tlb_fn(env, d2, i, addr + msize, oi, ra);
+                tlb_fn(env, d2, i, addr + msize, ra);
             }
             i += esize, pg >>= esize;
             addr += 2 * msize;
@@ -4736,9 +4693,8 @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr,
 static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
                       uint32_t desc, const uintptr_t ra,
                       const int esize, const int msize,
-                      sve_st1_tlb_fn *tlb_fn)
+                      sve_ldst1_tlb_fn *tlb_fn)
 {
-    const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
     const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
     intptr_t i, oprsz = simd_oprsz(desc);
     void *d1 = &env->vfp.zregs[rd];
@@ -4750,9 +4706,9 @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
         uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
         do {
             if (pg & 1) {
-                tlb_fn(env, d1, i, addr, oi, ra);
+                tlb_fn(env, d1, i, addr, ra);
-                tlb_fn(env, d2, i, addr + msize, oi, ra);
+                tlb_fn(env, d2, i, addr + msize, ra);
-                tlb_fn(env, d3, i, addr + 2 * msize, oi, ra);
+                tlb_fn(env, d3, i, addr + 2 * msize, ra);
             }
             i += esize, pg >>= esize;
             addr += 3 * msize;
@@ -4764,9 +4720,8 @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr,
 static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
                       uint32_t desc, const uintptr_t ra,
                       const int esize, const int msize,
-                      sve_st1_tlb_fn *tlb_fn)
+                      sve_ldst1_tlb_fn *tlb_fn)
 {
-    const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
     const unsigned rd = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 5);
     intptr_t i, oprsz = simd_oprsz(desc);
     void *d1 = &env->vfp.zregs[rd];
@@ -4779,10 +4734,10 @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr,
         uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));
         do {
             if (pg & 1) {
-                tlb_fn(env, d1, i, addr, oi, ra);
+                tlb_fn(env, d1, i, addr, ra);
-                tlb_fn(env, d2, i, addr + msize, oi, ra);
+                tlb_fn(env, d2, i, addr + msize, ra);
-                tlb_fn(env, d3, i, addr + 2 * msize, oi, ra);
+                tlb_fn(env, d3, i, addr + 2 * msize, ra);
-                tlb_fn(env, d4, i, addr + 3 * msize, oi, ra);
+                tlb_fn(env, d4, i, addr + 3 * msize, ra);
             }
             i += esize, pg >>= esize;
             addr += 4 * msize;
@@ -4878,9 +4833,8 @@ static target_ulong off_zd_d(void *reg, intptr_t reg_ofs)
 
 static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
                        target_ulong base, uint32_t desc, uintptr_t ra,
-                       zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
+                       zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
 {
-    const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
     const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
     intptr_t i, oprsz = simd_oprsz(desc);
     ARMVectorReg scratch = { };
@@ -4891,7 +4845,7 @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
         do {
             if (likely(pg & 1)) {
                 target_ulong off = off_fn(vm, i);
-                tlb_fn(env, &scratch, i, base + (off << scale), oi, ra);
+                tlb_fn(env, &scratch, i, base + (off << scale), ra);
             }
             i += 4, pg >>= 4;
         } while (i & 15);
@@ -4904,9 +4858,8 @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
 
 static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
                        target_ulong base, uint32_t desc, uintptr_t ra,
-                       zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
+                       zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
 {
-    const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
     const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
     intptr_t i, oprsz = simd_oprsz(desc) / 8;
     ARMVectorReg scratch = { };
@@ -4916,7 +4869,7 @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
         uint8_t pg = *(uint8_t *)(vg + H1(i));
         if (likely(pg & 1)) {
             target_ulong off = off_fn(vm, i * 8);
-            tlb_fn(env, &scratch, i * 8, base + (off << scale), oi, ra);
+            tlb_fn(env, &scratch, i * 8, base + (off << scale), ra);
         }
     }
     set_helper_retaddr(0);
@@ -5078,7 +5031,7 @@ DO_LD_NF(dd_be,      , uint64_t, uint64_t, ldq_be_p)
  */
 static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
                                 target_ulong base, uint32_t desc, uintptr_t ra,
-                                zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn,
+                                zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
                                 sve_ld1_nf_fn *nonfault_fn)
 {
     const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
@@ -5094,7 +5047,7 @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
         set_helper_retaddr(ra);
         addr = off_fn(vm, reg_off);
         addr = base + (addr << scale);
-        tlb_fn(env, vd, reg_off, addr, oi, ra);
+        tlb_fn(env, vd, reg_off, addr, ra);
 
         /* The rest of the reads will be non-faulting.  */
         set_helper_retaddr(0);
@@ -5120,7 +5073,7 @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
 
 static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
                                 target_ulong base, uint32_t desc, uintptr_t ra,
-                                zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn,
+                                zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn,
                                 sve_ld1_nf_fn *nonfault_fn)
 {
     const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
@@ -5136,7 +5089,7 @@ static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
         set_helper_retaddr(ra);
         addr = off_fn(vm, reg_off);
         addr = base + (addr << scale);
-        tlb_fn(env, vd, reg_off, addr, oi, ra);
+        tlb_fn(env, vd, reg_off, addr, ra);
 
         /* The rest of the reads will be non-faulting.  */
         set_helper_retaddr(0);
@@ -5246,9 +5199,8 @@ DO_LDFF1_ZPZ_D(dd_be, zd)
 
 static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
                        target_ulong base, uint32_t desc, uintptr_t ra,
-                       zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
+                       zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
 {
-    const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
     const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
     intptr_t i, oprsz = simd_oprsz(desc);
 
@@ -5258,7 +5210,7 @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
         do {
             if (likely(pg & 1)) {
                 target_ulong off = off_fn(vm, i);
-                tlb_fn(env, vd, i, base + (off << scale), oi, ra);
+                tlb_fn(env, vd, i, base + (off << scale), ra);
             }
             i += 4, pg >>= 4;
         } while (i & 15);
@@ -5268,9 +5220,8 @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
 
 static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
                        target_ulong base, uint32_t desc, uintptr_t ra,
-                       zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn)
+                       zreg_off_fn *off_fn, sve_ldst1_tlb_fn *tlb_fn)
 {
-    const TCGMemOpIdx oi = extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHIFT);
     const int scale = extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, 2);
     intptr_t i, oprsz = simd_oprsz(desc) / 8;
 
@@ -5279,7 +5230,7 @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
         uint8_t pg = *(uint8_t *)(vg + H1(i));
         if (likely(pg & 1)) {
             target_ulong off = off_fn(vm, i * 8);
-            tlb_fn(env, vd, i * 8, base + (off << scale), oi, ra);
+            tlb_fn(env, vd, i * 8, base + (off << scale), ra);
         }
     }
     set_helper_retaddr(0);

qemu/x86_64.h

@@ -303,6 +303,61 @@
 #define cpu_ldl_code cpu_ldl_code_x86_64
 #define cpu_ldub_code cpu_ldub_code_x86_64
 #define cpu_lduw_code cpu_lduw_code_x86_64
+#define cpu_ldub_code cpu_ldub_code_x86_64
+#define cpu_lduw_code cpu_lduw_code_x86_64
+#define cpu_ldl_code cpu_ldl_code_x86_64
+#define cpu_ldq_code cpu_ldq_code_x86_64
+#define cpu_ldub_mmuidx_ra cpu_ldub_mmuidx_ra_x86_64
+#define cpu_ldsb_mmuidx_ra cpu_ldsb_mmuidx_ra_x86_64
+#define cpu_lduw_be_mmuidx_ra cpu_lduw_be_mmuidx_ra_x86_64
+#define cpu_ldsw_be_mmuidx_ra cpu_ldsw_be_mmuidx_ra_x86_64
+#define cpu_ldl_be_mmuidx_ra cpu_ldl_be_mmuidx_ra_x86_64
+#define cpu_ldq_be_mmuidx_ra cpu_ldq_be_mmuidx_ra_x86_64
+#define cpu_lduw_le_mmuidx_ra cpu_lduw_le_mmuidx_ra_x86_64
+#define cpu_ldsw_le_mmuidx_ra cpu_ldsw_le_mmuidx_ra_x86_64
+#define cpu_ldl_le_mmuidx_ra cpu_ldl_le_mmuidx_ra_x86_64
+#define cpu_ldq_le_mmuidx_ra cpu_ldq_le_mmuidx_ra_x86_64
+#define cpu_stb_mmuidx_ra cpu_stb_mmuidx_ra_x86_64
+#define cpu_stw_be_mmuidx_ra cpu_stw_be_mmuidx_ra_x86_64
+#define cpu_stl_be_mmuidx_ra cpu_stl_be_mmuidx_ra_x86_64
+#define cpu_stq_be_mmuidx_ra cpu_stq_be_mmuidx_ra_x86_64
+#define cpu_stw_le_mmuidx_ra cpu_stw_le_mmuidx_ra_x86_64
+#define cpu_stl_le_mmuidx_ra cpu_stl_le_mmuidx_ra_x86_64
+#define cpu_stq_le_mmuidx_ra cpu_stq_le_mmuidx_ra_x86_64
+#define cpu_ldub_data cpu_ldub_data_x86_64
+#define cpu_ldsb_data cpu_ldsb_data_x86_64
+#define cpu_lduw_be_data cpu_lduw_be_data_x86_64
+#define cpu_ldsw_be_data cpu_ldsw_be_data_x86_64
+#define cpu_ldl_be_data cpu_ldl_be_data_x86_64
+#define cpu_ldq_be_data cpu_ldq_be_data_x86_64
+#define cpu_lduw_le_data cpu_lduw_le_data_x86_64
+#define cpu_ldsw_le_data cpu_ldsw_le_data_x86_64
+#define cpu_ldl_le_data cpu_ldl_le_data_x86_64
+#define cpu_ldq_le_data cpu_ldq_le_data_x86_64
+#define cpu_ldub_data_ra cpu_ldub_data_ra_x86_64
+#define cpu_ldsb_data_ra cpu_ldsb_data_ra_x86_64
+#define cpu_lduw_be_data_ra cpu_lduw_be_data_ra_x86_64
+#define cpu_ldsw_be_data_ra cpu_ldsw_be_data_ra_x86_64
+#define cpu_ldl_be_data_ra cpu_ldl_be_data_ra_x86_64
+#define cpu_ldq_be_data_ra cpu_ldq_be_data_ra_x86_64
+#define cpu_lduw_le_data_ra cpu_lduw_le_data_ra_x86_64
+#define cpu_ldsw_le_data_ra cpu_ldsw_le_data_ra_x86_64
+#define cpu_ldl_le_data_ra cpu_ldl_le_data_ra_x86_64
+#define cpu_ldq_le_data_ra cpu_ldq_le_data_ra_x86_64
+#define cpu_stb_data cpu_stb_data_x86_64
+#define cpu_stw_be_data cpu_stw_be_data_x86_64
+#define cpu_stl_be_data cpu_stl_be_data_x86_64
+#define cpu_stq_be_data cpu_stq_be_data_x86_64
+#define cpu_stw_le_data cpu_stw_le_data_x86_64
+#define cpu_stl_le_data cpu_stl_le_data_x86_64
+#define cpu_stq_le_data cpu_stq_le_data_x86_64
+#define cpu_stb_data_ra cpu_stb_data_ra_x86_64
+#define cpu_stw_be_data_ra cpu_stw_be_data_ra_x86_64
+#define cpu_stl_be_data_ra cpu_stl_be_data_ra_x86_64
+#define cpu_stq_be_data_ra cpu_stq_be_data_ra_x86_64
+#define cpu_stw_le_data_ra cpu_stw_le_data_ra_x86_64
+#define cpu_stl_le_data_ra cpu_stl_le_data_ra_x86_64
+#define cpu_stq_le_data_ra cpu_stq_le_data_ra_x86_64
 #define cpu_loop_exit cpu_loop_exit_x86_64
 #define cpu_loop_exit_atomic cpu_loop_exit_atomic_x86_64
 #define cpu_loop_exit_noexc cpu_loop_exit_noexc_x86_64