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target-arm: Add TPIDR_EL2
Backports commit ff05f37babe7874f28dcead6e9e4f1904d35a13a from qemu
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parent
0374ab0421
commit
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@ -2184,6 +2184,8 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = {
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PL2_RW, 0, NULL, 0 },
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PL2_RW, 0, NULL, 0 },
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{ "SCTLR_EL2", 0,1,0, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
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{ "SCTLR_EL2", 0,1,0, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
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PL2_RW, 0, NULL, 0 },
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PL2_RW, 0, NULL, 0 },
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{ "TPIDR_EL2", 0,13,0, 3,4,2, ARM_CP_STATE_BOTH, ARM_CP_CONST,
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PL2_RW, 0, NULL, 0 },
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REGINFO_SENTINEL
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REGINFO_SENTINEL
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};
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};
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@ -2247,6 +2249,8 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
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{ "SCTLR_EL2", 0,1,0, 3,4,0, ARM_CP_STATE_BOTH, 0,
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{ "SCTLR_EL2", 0,1,0, 3,4,0, ARM_CP_STATE_BOTH, 0,
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PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.sctlr_el[2]), {0, 0},
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PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.sctlr_el[2]), {0, 0},
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NULL, NULL, sctlr_write, NULL, raw_write },
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NULL, NULL, sctlr_write, NULL, raw_write },
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{ "TPIDR_EL2", 0,13,0, 3,4,2, ARM_CP_STATE_BOTH, 0,
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PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.tpidr_el[2]) },
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REGINFO_SENTINEL
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REGINFO_SENTINEL
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};
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};
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