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target/mips: Switch to do_transaction_failed() hook

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Switch the MIPS target from the old unassigned_access hook to the new
do_transaction_failed hook.

Unlike the old hook, do_transaction_failed is only ever called from
the TCG memory access paths, so there is no need for the "ignore this
if we're using KVM" hack that we were previously using to work around
the way unassigned_access was called for all kinds of memory accesses
to unassigned physical addresses.

The MIPS target does not ever do direct memory reads by physical
address (via either ldl_phys etc or address_space_ldl etc), so the
only memory accesses this affects are the 'normal' guest loads and
stores, which will be handled by the new hook; their behaviour is
unchanged.

Backports commit 4f02a06d50ef0081089ed8cb3ec7c7986e3c95f8 from qemu
This commit is contained in:
Peter Maydell 2019-11-20 13:08:04 -05:00 committed by Lioncash
parent 3c0bab6b11
commit 2faffb5af1
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
8 changed files with 19 additions and 15 deletions
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2
qemu/header_gen.py
View file

@ -5441,13 +5441,13 @@ mips_symbols = (
'ieee_ex_to_mips',
'ieee_rm',
'mips_cpu_do_interrupt',
'mips_cpu_do_transaction_failed',
'mips_cpu_do_unaligned_access',
'mips_cpu_exec_interrupt',
'mips_cpu_get_phys_page_debug',
'mips_cpu_list',
'mips_cpu_register_types',
'mips_cpu_tlb_fill',
'mips_cpu_unassigned_access',
'mips_defs',
'mips_defs_number',
'mips_machine_init_register_types',

2
qemu/mips.h
View file

@ -4327,13 +4327,13 @@
#define ieee_ex_to_mips ieee_ex_to_mips_mips
#define ieee_rm ieee_rm_mips
#define mips_cpu_do_interrupt mips_cpu_do_interrupt_mips
#define mips_cpu_do_transaction_failed mips_cpu_do_transaction_failed_mips
#define mips_cpu_do_unaligned_access mips_cpu_do_unaligned_access_mips
#define mips_cpu_exec_interrupt mips_cpu_exec_interrupt_mips
#define mips_cpu_get_phys_page_debug mips_cpu_get_phys_page_debug_mips
#define mips_cpu_list mips_cpu_list_mips
#define mips_cpu_register_types mips_cpu_register_types_mips
#define mips_cpu_tlb_fill mips_cpu_tlb_fill_mips
#define mips_cpu_unassigned_access mips_cpu_unassigned_access_mips
#define mips_defs mips_defs_mips
#define mips_defs_number mips_defs_number_mips
#define mips_machine_init_register_types mips_machine_init_register_types_mips

2
qemu/mips64.h
View file

@ -4327,13 +4327,13 @@
#define ieee_ex_to_mips ieee_ex_to_mips_mips64
#define ieee_rm ieee_rm_mips64
#define mips_cpu_do_interrupt mips_cpu_do_interrupt_mips64
#define mips_cpu_do_transaction_failed mips_cpu_do_transaction_failed_mips64
#define mips_cpu_do_unaligned_access mips_cpu_do_unaligned_access_mips64
#define mips_cpu_exec_interrupt mips_cpu_exec_interrupt_mips64
#define mips_cpu_get_phys_page_debug mips_cpu_get_phys_page_debug_mips64
#define mips_cpu_list mips_cpu_list_mips64
#define mips_cpu_register_types mips_cpu_register_types_mips64
#define mips_cpu_tlb_fill mips_cpu_tlb_fill_mips64
#define mips_cpu_unassigned_access mips_cpu_unassigned_access_mips64
#define mips_defs mips_defs_mips64
#define mips_defs_number mips_defs_number_mips64
#define mips_machine_init_register_types mips_machine_init_register_types_mips64

2
qemu/mips64el.h
View file

@ -4327,13 +4327,13 @@
#define ieee_ex_to_mips ieee_ex_to_mips_mips64el
#define ieee_rm ieee_rm_mips64el
#define mips_cpu_do_interrupt mips_cpu_do_interrupt_mips64el
#define mips_cpu_do_transaction_failed mips_cpu_do_transaction_failed_mips64el
#define mips_cpu_do_unaligned_access mips_cpu_do_unaligned_access_mips64el
#define mips_cpu_exec_interrupt mips_cpu_exec_interrupt_mips64el
#define mips_cpu_get_phys_page_debug mips_cpu_get_phys_page_debug_mips64el
#define mips_cpu_list mips_cpu_list_mips64el
#define mips_cpu_register_types mips_cpu_register_types_mips64el
#define mips_cpu_tlb_fill mips_cpu_tlb_fill_mips64el
#define mips_cpu_unassigned_access mips_cpu_unassigned_access_mips64el
#define mips_defs mips_defs_mips64el
#define mips_defs_number mips_defs_number_mips64el
#define mips_machine_init_register_types mips_machine_init_register_types_mips64el

2
qemu/mipsel.h
View file

@ -4327,13 +4327,13 @@
#define ieee_ex_to_mips ieee_ex_to_mips_mipsel
#define ieee_rm ieee_rm_mipsel
#define mips_cpu_do_interrupt mips_cpu_do_interrupt_mipsel
#define mips_cpu_do_transaction_failed mips_cpu_do_transaction_failed_mipsel
#define mips_cpu_do_unaligned_access mips_cpu_do_unaligned_access_mipsel
#define mips_cpu_exec_interrupt mips_cpu_exec_interrupt_mipsel
#define mips_cpu_get_phys_page_debug mips_cpu_get_phys_page_debug_mipsel
#define mips_cpu_list mips_cpu_list_mipsel
#define mips_cpu_register_types mips_cpu_register_types_mipsel
#define mips_cpu_tlb_fill mips_cpu_tlb_fill_mipsel
#define mips_cpu_unassigned_access mips_cpu_unassigned_access_mipsel
#define mips_defs mips_defs_mipsel
#define mips_defs_number mips_defs_number_mipsel
#define mips_machine_init_register_types mips_machine_init_register_types_mipsel

2
qemu/target/mips/cpu.c
View file

@ -176,7 +176,7 @@ static void mips_cpu_class_init(struct uc_struct *uc, ObjectClass *c, void *data
cc->set_pc = mips_cpu_set_pc;
cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
#ifndef CONFIG_USER_ONLY
cc->do_unassigned_access = mips_cpu_unassigned_access;
cc->do_transaction_failed = mips_cpu_do_transaction_failed;
cc->do_unaligned_access = mips_cpu_do_unaligned_access;
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
#endif

8
qemu/target/mips/internal.h
View file

@ -140,9 +140,11 @@ void r4k_helper_tlbinv(CPUMIPSState *env);
void r4k_helper_tlbinvf(CPUMIPSState *env);
void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
bool is_write, bool is_exec, int unused,
unsigned size);
void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
int rw);
#endif

14
qemu/target/mips/op_helper.c
View file

@ -2655,9 +2655,11 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
do_raise_exception_err(env, excp, error_code, retaddr);
}
void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
bool is_write, bool is_exec, int unused,
unsigned size)
void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr)
{
MIPSCPU *cpu = MIPS_CPU(cs->uc, cs);
CPUMIPSState *env = &cpu->env;
@ -2668,10 +2670,10 @@ void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
* Until we can trigger a bus error exception through KVM lets just ignore
* the access.
*/
if (is_exec) {
raise_exception(env, EXCP_IBE);
if (access_type == MMU_INST_FETCH) {
do_raise_exception(env, EXCP_IBE, retaddr);
} else {
raise_exception(env, EXCP_DBE);
do_raise_exception(env, EXCP_DBE, retaddr);
}
}
#endif /* !CONFIG_USER_ONLY */