yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-03-08 10:09:43 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: Pass in current_el to fp and sve_exception_el

Browse source 
We are going to want to determine whether sve is enabled
for EL other than current.

Backports commit 2de7ace292cf7846b0cda0e940272d2cb0e06859 from qemu
This commit is contained in:
Richard Henderson 2018-10-08 11:15:46 -04:00 committed by Lioncash
parent 00fc5d43fd
commit 2fb9c4c41d
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 9 additions and 12 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

21
qemu/target/arm/helper.c
View file

@ -3831,12 +3831,10 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
* take care of raising that exception.
* C.f. the ARM pseudocode function CheckSVEEnabled.
*/
static int sve_exception_el(CPUARMState *env)
static int sve_exception_el(CPUARMState *env, int el)
{
#ifndef CONFIG_USER_ONLY
unsigned current_el = arm_current_el(env);
if (current_el <= 1) {
if (el <= 1) {
bool disabled = false;
/* The CPACR.ZEN controls traps to EL1:
@ -3847,7 +3845,7 @@ static int sve_exception_el(CPUARMState *env)
if (!extract32(env->cp15.cpacr_el1, 16, 1)) {
disabled = true;
} else if (!extract32(env->cp15.cpacr_el1, 17, 1)) {
disabled = current_el == 0;
disabled = el == 0;
}
if (disabled) {
/* route_to_el2 */
@ -3860,7 +3858,7 @@ static int sve_exception_el(CPUARMState *env)
if (!extract32(env->cp15.cpacr_el1, 20, 1)) {
disabled = true;
} else if (!extract32(env->cp15.cpacr_el1, 21, 1)) {
disabled = current_el == 0;
disabled = el == 0;
}
if (disabled) {
return 0;
@ -3870,7 +3868,7 @@ static int sve_exception_el(CPUARMState *env)
/* CPTR_EL2. Since TZ and TFP are positive,
* they will be zero when EL2 is not present.
*/
if (current_el <= 2 && !arm_is_secure_below_el3(env)) {
if (el <= 2 && !arm_is_secure_below_el3(env)) {
if (env->cp15.cptr_el[2] & CPTR_TZ) {
return 2;
}
@ -11742,11 +11740,10 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
/* Return the exception level to which FP-disabled exceptions should
* be taken, or 0 if FP is enabled.
*/
static inline int fp_exception_el(CPUARMState *env)
static int fp_exception_el(CPUARMState *env, int cur_el)
{
#ifndef CONFIG_USER_ONLY
int fpen;
int cur_el = arm_current_el(env);
/* CPACR and the CPTR registers don't exist before v6, so FP is
* always accessible
@ -11809,7 +11806,8 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *pflags)
{
ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
int fp_el = fp_exception_el(env);
int current_el = arm_current_el(env);
int fp_el = fp_exception_el(env, current_el);
uint32_t flags;
if (is_a64(env)) {
@ -11820,7 +11818,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT);
if (arm_feature(env, ARM_FEATURE_SVE)) {
int sve_el = sve_exception_el(env);
int sve_el = sve_exception_el(env, current_el);
uint32_t zcr_len;
/* If SVE is disabled, but FP is enabled,
@ -11829,7 +11827,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
if (sve_el != 0 && fp_el == 0) {
zcr_len = 0;
} else {
int current_el = arm_current_el(env);
ARMCPU *cpu = arm_env_get_cpu(env);
zcr_len = cpu->sve_max_vq - 1;