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tcg/arm: Handle ctz and clz opcodes

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Backports commit cc0fec8a4d2a8546fe236a09bfd80150af9cbe6b from qemu
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Richard Henderson 2018-03-01 16:20:45 -05:00 committed by Lioncash
parent 2b87ddda35
commit 303fc987ed
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 29 additions and 2 deletions
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4
qemu/tcg/arm/tcg-target.h
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@ -111,8 +111,8 @@ extern bool use_idiv_instructions_rt;
#define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0 #define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_clz_i32 0 #define TCG_TARGET_HAS_clz_i32 use_armv5t_instructions
#define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_ctz_i32 use_armv7_instructions
#define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions #define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
#define TCG_TARGET_HAS_extract_i32 use_armv7_instructions #define TCG_TARGET_HAS_extract_i32 use_armv7_instructions
#define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions #define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions

27
qemu/tcg/arm/tcg-target.inc.c
View file

@ -266,6 +266,9 @@ typedef enum {
ARITH_BIC = 0xe << 21, ARITH_BIC = 0xe << 21,
ARITH_MVN = 0xf << 21, ARITH_MVN = 0xf << 21,
INSN_CLZ = 0x016f0f10,
INSN_RBIT = 0x06ff0f30,
INSN_LDR_IMM = 0x04100000, INSN_LDR_IMM = 0x04100000,
INSN_LDR_REG = 0x06100000, INSN_LDR_REG = 0x06100000,
INSN_STR_IMM = 0x04000000, INSN_STR_IMM = 0x04000000,
@ -1838,6 +1841,28 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
} }
break; break;
case INDEX_op_ctz_i32:
tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, args[1], 0);
a1 = TCG_REG_TMP;
goto do_clz;
case INDEX_op_clz_i32:
a1 = args[1];
do_clz:
a0 = args[0];
a2 = args[2];
c = const_args[2];
if (c && a2 == 32) {
tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0);
break;
}
tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0);
tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0);
if (c || a0 != a2) {
tcg_out_dat_rIK(s, COND_EQ, ARITH_MOV, ARITH_MVN, a0, 0, a2, c);
}
break;
case INDEX_op_brcond_i32: case INDEX_op_brcond_i32:
tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0,
args[0], args[1], const_args[1]); args[0], args[1], const_args[1]);
@ -1972,6 +1997,8 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_sar_i32, { "r", "r", "ri" } }, { INDEX_op_sar_i32, { "r", "r", "ri" } },
{ INDEX_op_rotl_i32, { "r", "r", "ri" } }, { INDEX_op_rotl_i32, { "r", "r", "ri" } },
{ INDEX_op_rotr_i32, { "r", "r", "ri" } }, { INDEX_op_rotr_i32, { "r", "r", "ri" } },
{ INDEX_op_clz_i32, { "r", "r", "rIK" } },
{ INDEX_op_ctz_i32, { "r", "r", "rIK" } },
{ INDEX_op_brcond_i32, { "r", "rIN" } }, { INDEX_op_brcond_i32, { "r", "rIN" } },
{ INDEX_op_setcond_i32, { "r", "r", "rIN" } }, { INDEX_op_setcond_i32, { "r", "r", "rIN" } },