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tcg/arm: Handle ctz and clz opcodes
Backports commit cc0fec8a4d2a8546fe236a09bfd80150af9cbe6b from qemu
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2b87ddda35
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@ -111,8 +111,8 @@ extern bool use_idiv_instructions_rt;
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#define TCG_TARGET_HAS_eqv_i32 0
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#define TCG_TARGET_HAS_nand_i32 0
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#define TCG_TARGET_HAS_nor_i32 0
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#define TCG_TARGET_HAS_clz_i32 0
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#define TCG_TARGET_HAS_ctz_i32 0
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#define TCG_TARGET_HAS_clz_i32 use_armv5t_instructions
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#define TCG_TARGET_HAS_ctz_i32 use_armv7_instructions
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#define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
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#define TCG_TARGET_HAS_extract_i32 use_armv7_instructions
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#define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions
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@ -266,6 +266,9 @@ typedef enum {
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ARITH_BIC = 0xe << 21,
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ARITH_MVN = 0xf << 21,
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INSN_CLZ = 0x016f0f10,
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INSN_RBIT = 0x06ff0f30,
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INSN_LDR_IMM = 0x04100000,
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INSN_LDR_REG = 0x06100000,
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INSN_STR_IMM = 0x04000000,
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@ -1838,6 +1841,28 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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}
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break;
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case INDEX_op_ctz_i32:
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tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, args[1], 0);
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a1 = TCG_REG_TMP;
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goto do_clz;
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case INDEX_op_clz_i32:
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a1 = args[1];
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do_clz:
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a0 = args[0];
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a2 = args[2];
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c = const_args[2];
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if (c && a2 == 32) {
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tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0);
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break;
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}
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tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0);
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tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0);
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if (c || a0 != a2) {
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tcg_out_dat_rIK(s, COND_EQ, ARITH_MOV, ARITH_MVN, a0, 0, a2, c);
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}
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break;
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case INDEX_op_brcond_i32:
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tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0,
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args[0], args[1], const_args[1]);
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@ -1972,6 +1997,8 @@ static const TCGTargetOpDef arm_op_defs[] = {
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{ INDEX_op_sar_i32, { "r", "r", "ri" } },
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{ INDEX_op_rotl_i32, { "r", "r", "ri" } },
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{ INDEX_op_rotr_i32, { "r", "r", "ri" } },
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{ INDEX_op_clz_i32, { "r", "r", "rIK" } },
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{ INDEX_op_ctz_i32, { "r", "r", "rIK" } },
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{ INDEX_op_brcond_i32, { "r", "rIN" } },
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{ INDEX_op_setcond_i32, { "r", "r", "rIN" } },
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