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RISC-V: Fixes to CSR_* register macros.

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This adds some missing CSR_* register macros, and documents some as being
priv v1.9.1 specific.

Backports commit 8e73df6aa3f2f0e5c26c03a94a88406616291815 from qemu
This commit is contained in:
Jim Wilson 2019-03-19 23:39:28 -04:00 committed by Lioncash
parent c0f036578c
commit 30ab335bb3
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 33 additions and 2 deletions
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35
qemu/target/riscv/cpu_bits.h
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@ -135,16 +135,22 @@
/* Legacy Counter Setup (priv v1.9.1) */ /* Legacy Counter Setup (priv v1.9.1) */
#define CSR_MUCOUNTEREN 0x320 #define CSR_MUCOUNTEREN 0x320
#define CSR_MSCOUNTEREN 0x321 #define CSR_MSCOUNTEREN 0x321
#define CSR_MHCOUNTEREN 0x322
/* Machine Trap Handling */ /* Machine Trap Handling */
#define CSR_MSCRATCH 0x340 #define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341 #define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342 #define CSR_MCAUSE 0x342
#define CSR_MBADADDR 0x343 #define CSR_MTVAL 0x343
#define CSR_MIP 0x344 #define CSR_MIP 0x344
/* Legacy Machine Trap Handling (priv v1.9.1) */
#define CSR_MBADADDR 0x343
/* Supervisor Trap Setup */ /* Supervisor Trap Setup */
#define CSR_SSTATUS 0x100 #define CSR_SSTATUS 0x100
#define CSR_SEDELEG 0x102
#define CSR_SIDELEG 0x103
#define CSR_SIE 0x104 #define CSR_SIE 0x104
#define CSR_STVEC 0x105 #define CSR_STVEC 0x105
#define CSR_SCOUNTEREN 0x106 #define CSR_SCOUNTEREN 0x106
@ -153,9 +159,12 @@
#define CSR_SSCRATCH 0x140 #define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141 #define CSR_SEPC 0x141
#define CSR_SCAUSE 0x142 #define CSR_SCAUSE 0x142
#define CSR_SBADADDR 0x143 #define CSR_STVAL 0x143
#define CSR_SIP 0x144 #define CSR_SIP 0x144
/* Legacy Supervisor Trap Handling (priv v1.9.1) */
#define CSR_SBADADDR 0x143
/* Supervisor Protection and Translation */ /* Supervisor Protection and Translation */
#define CSR_SPTBR 0x180 #define CSR_SPTBR 0x180
#define CSR_SATP 0x180 #define CSR_SATP 0x180
@ -282,6 +291,28 @@
#define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER30H 0xb9e
#define CSR_MHPMCOUNTER31H 0xb9f #define CSR_MHPMCOUNTER31H 0xb9f
/* Legacy Hypervisor Trap Setup (priv v1.9.1) */
#define CSR_HSTATUS 0x200
#define CSR_HEDELEG 0x202
#define CSR_HIDELEG 0x203
#define CSR_HIE 0x204
#define CSR_HTVEC 0x205
/* Legacy Hypervisor Trap Handling (priv v1.9.1) */
#define CSR_HSCRATCH 0x240
#define CSR_HEPC 0x241
#define CSR_HCAUSE 0x242
#define CSR_HBADADDR 0x243
#define CSR_HIP 0x244
/* Legacy Machine Protection and Translation (priv v1.9.1) */
#define CSR_MBASE 0x380
#define CSR_MBOUND 0x381
#define CSR_MIBASE 0x382
#define CSR_MIBOUND 0x383
#define CSR_MDBASE 0x384
#define CSR_MDBOUND 0x385
/* mstatus CSR bits */ /* mstatus CSR bits */
#define MSTATUS_UIE 0x00000001 #define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002 #define MSTATUS_SIE 0x00000002