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target/arm: Correct store of FPSCR value via FPCXT_S

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In commit 64f863baeedc8659 we implemented the v8.1M FPCXT_S register,
but we got the write behaviour wrong. On read, this register reads
bits [27:0] of FPSCR plus the CONTROL.SFPA bit. On write, it doesn't
just write back those bits -- it writes a value to the whole FPSCR,
whose upper 4 bits are zeroes.

We also incorrectly implemented the write-to-FPSCR as a simple store
to vfp.xregs; this skips the "update the softfloat flags" part of
the vfp_set_fpscr helper so the value would read back correctly but
not actually take effect.

Fix both of these things by doing a complete write to the FPSCR
using the helper function.

Backports 7fbf95a037d79c5e923ffb51ac902dbe9599c87f
This commit is contained in:
Peter Maydell 2021-03-03 19:57:40 -05:00 committed by Lioncash
parent 85b417d438
commit 311b6fd74c
1 changed files with 6 additions and 6 deletions
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12
qemu/target/arm/translate-vfp.inc.c
View file

@ -734,8 +734,11 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
} }
case ARM_VFP_FPCXT_S: case ARM_VFP_FPCXT_S:
{ {
TCGv_i32 sfpa, control, fpscr; TCGv_i32 sfpa, control;
/* Set FPSCR[27:0] and CONTROL.SFPA from value */ /*
* Set FPSCR and CONTROL.SFPA from value; the new FPSCR takes
* bits [27:0] from value and zeroes bits [31:28].
*/
tmp = loadfn(s, opaque); tmp = loadfn(s, opaque);
sfpa = tcg_temp_new_i32(tcg_ctx); sfpa = tcg_temp_new_i32(tcg_ctx);
tcg_gen_shri_i32(tcg_ctx, sfpa, tmp, 31); tcg_gen_shri_i32(tcg_ctx, sfpa, tmp, 31);
@ -743,11 +746,8 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
tcg_gen_deposit_i32(tcg_ctx, control, control, sfpa, tcg_gen_deposit_i32(tcg_ctx, control, control, sfpa,
R_V7M_CONTROL_SFPA_SHIFT, 1); R_V7M_CONTROL_SFPA_SHIFT, 1);
store_cpu_field(s, control, v7m.control[M_REG_S]); store_cpu_field(s, control, v7m.control[M_REG_S]);
fpscr = load_cpu_field(s, vfp.xregs[ARM_VFP_FPSCR]);
tcg_gen_andi_i32(tcg_ctx, fpscr, fpscr, FPCR_NZCV_MASK);
tcg_gen_andi_i32(tcg_ctx, tmp, tmp, ~FPCR_NZCV_MASK); tcg_gen_andi_i32(tcg_ctx, tmp, tmp, ~FPCR_NZCV_MASK);
tcg_gen_or_i32(tcg_ctx, fpscr, fpscr, tmp); gen_helper_vfp_set_fpscr(tcg_ctx, tcg_ctx->cpu_env, tmp);
store_cpu_field(s, fpscr, vfp.xregs[ARM_VFP_FPSCR]);
tcg_temp_free_i32(tcg_ctx, tmp); tcg_temp_free_i32(tcg_ctx, tmp);
tcg_temp_free_i32(tcg_ctx, sfpa); tcg_temp_free_i32(tcg_ctx, sfpa);
break; break;