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target/arm: Split out gen_gvec_fn_zz

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Model the new function on gen_gvec_fn2 in translate-a64.c, but
indicating which kind of register and in which order. Since there
is only one user of do_vector2_z, fold it into do_mov_z

Backports f7d79c41fa4bd0f0d27dcd14babab8575fbed39f
This commit is contained in:
Richard Henderson 2021-02-26 13:48:01 -05:00 committed by Lioncash
parent 234a22803d
commit 3146cbb64e
1 changed files with 10 additions and 10 deletions
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10
qemu/target/arm/translate-sve.c
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@ -140,17 +140,14 @@ static int pred_gvec_reg_size(DisasContext *s)
} }
/* Invoke a vector expander on two Zregs. */ /* Invoke a vector expander on two Zregs. */
static bool do_vector2_z(DisasContext *s, GVecGen2Fn *gvec_fn, static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
int esz, int rd, int rn) int esz, int rd, int rn)
{ {
if (sve_access_check(s)) {
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned vsz = vec_full_reg_size(s); unsigned vsz = vec_full_reg_size(s);
gvec_fn(tcg_ctx, esz, vec_full_reg_offset(s, rd), gvec_fn(tcg_ctx, esz, vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn), vsz, vsz); vec_full_reg_offset(s, rn), vsz, vsz);
} }
return true;
}
/* Invoke a vector expander on three Zregs. */ /* Invoke a vector expander on three Zregs. */
static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn, static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn,
@ -169,7 +166,10 @@ static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn,
/* Invoke a vector move on two Zregs. */ /* Invoke a vector move on two Zregs. */
static bool do_mov_z(DisasContext *s, int rd, int rn) static bool do_mov_z(DisasContext *s, int rd, int rn)
{ {
return do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn); if (sve_access_check(s)) {
gen_gvec_fn_zz(s, tcg_gen_gvec_mov, MO_8, rd, rn);
}
return true;
} }
/* Initialize a Zreg with replications of a 64-bit immediate. */ /* Initialize a Zreg with replications of a 64-bit immediate. */