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target/arm: Split out gen_gvec_fn_zz
Model the new function on gen_gvec_fn2 in translate-a64.c, but indicating which kind of register and in which order. Since there is only one user of do_vector2_z, fold it into do_mov_z Backports f7d79c41fa4bd0f0d27dcd14babab8575fbed39f
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@ -140,17 +140,14 @@ static int pred_gvec_reg_size(DisasContext *s)
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}
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/* Invoke a vector expander on two Zregs. */
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static bool do_vector2_z(DisasContext *s, GVecGen2Fn *gvec_fn,
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static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
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int esz, int rd, int rn)
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{
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if (sve_access_check(s)) {
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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unsigned vsz = vec_full_reg_size(s);
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gvec_fn(tcg_ctx, esz, vec_full_reg_offset(s, rd),
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vec_full_reg_offset(s, rn), vsz, vsz);
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}
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return true;
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}
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/* Invoke a vector expander on three Zregs. */
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static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn,
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@ -169,7 +166,10 @@ static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn,
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/* Invoke a vector move on two Zregs. */
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static bool do_mov_z(DisasContext *s, int rd, int rn)
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{
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return do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn);
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if (sve_access_check(s)) {
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gen_gvec_fn_zz(s, tcg_gen_gvec_mov, MO_8, rd, rn);
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}
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return true;
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}
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/* Initialize a Zreg with replications of a 64-bit immediate. */
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