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m68k: improve cpu instantiation comments
Improvement in comments for the instantiation functions. This is to highlight what each cpu class, in the 68000 series, contains in terms of instructions/features. Backports ee2fc6c6da8b2d6f961c8559d62e990c65f67736
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@ -99,6 +99,7 @@ static void m5206_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
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m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
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}
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}
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/* Base feature set, including isns. for m68k family */
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static void m68000_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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static void m68000_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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{
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{
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M68kCPU *cpu = M68K_CPU(uc, obj);
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M68kCPU *cpu = M68K_CPU(uc, obj);
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@ -131,6 +132,13 @@ static void m680x0_cpu_common(CPUM68KState *env)
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m68k_set_feature(env, M68K_FEATURE_MOVEP);
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m68k_set_feature(env, M68K_FEATURE_MOVEP);
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}
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}
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/*
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* Adds BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO, BFINS, BFSET, BFTST, CAS, CAS2,
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* CHK2, CMP2, DIVSL, DIVUL, EXTB, PACK, TRAPcc, UNPK.
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*
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* 68020/30 only:
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* CALLM, cpBcc, cpDBcc, cpGEN, cpRESTORE, cpSAVE, cpScc, cpTRAPcc
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*/
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static void m68020_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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static void m68020_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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{
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{
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M68kCPU *cpu = M68K_CPU(uc, obj);
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M68kCPU *cpu = M68K_CPU(uc, obj);
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@ -140,6 +148,14 @@ static void m68020_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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m68k_set_feature(env, M68K_FEATURE_M68020);
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m68k_set_feature(env, M68K_FEATURE_M68020);
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}
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}
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/*
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* Adds: PFLUSH (*5)
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* 68030 Only: PFLUSHA (*5), PLOAD (*5), PMOVE
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* 68030/40 Only: PTEST
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*
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* NOTES:
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* 5. Not valid on MC68EC030
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*/
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static void m68030_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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static void m68030_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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{
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{
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M68kCPU *cpu = M68K_CPU(uc, obj);
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M68kCPU *cpu = M68K_CPU(uc, obj);
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@ -149,6 +165,23 @@ static void m68030_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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m68k_set_feature(env, M68K_FEATURE_M68030);
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m68k_set_feature(env, M68K_FEATURE_M68030);
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}
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}
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/*
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* Adds: CINV, CPUSH
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* Adds all with Note *2: FABS, FSABS, FDABS, FADD, FSADD, FDADD, FBcc, FCMP,
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* FDBcc, FDIV, FSDIV, FDDIV, FMOVE, FSMOVE, FDMOVE,
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* FMOVEM, FMUL, FSMUL, FDMUL, FNEG, FSNEG, FDNEG, FNOP,
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* FRESTORE, FSAVE, FScc, FSQRT, FSSQRT, FDSQRT, FSUB,
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* FSSUB, FDSUB, FTRAPcc, FTST
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*
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* Adds with Notes *2, and *3: FACOS, FASIN, FATAN, FATANH, FCOS, FCOSH, FETOX,
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* FETOXM, FGETEXP, FGETMAN, FINT, FINTRZ, FLOG10,
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* FLOG2, FLOGN, FLOGNP1, FMOD, FMOVECR, FREM,
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* FSCALE, FSGLDIV, FSGLMUL, FSIN, FSINCOS, FSINH,
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* FTAN, FTANH, FTENTOX, FTWOTOX
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* NOTES:
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* 2. Not applicable to the MC68EC040, MC68LC040, MC68EC060, and MC68LC060.
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* 3. These are software-supported instructions on the MC68040 and MC68060.
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*/
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static void m68040_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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static void m68040_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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{
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{
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M68kCPU *cpu = M68K_CPU(uc, obj);
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M68kCPU *cpu = M68K_CPU(uc, obj);
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@ -158,6 +191,17 @@ static void m68040_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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m68k_set_feature(env, M68K_FEATURE_M68040);
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m68k_set_feature(env, M68K_FEATURE_M68040);
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}
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}
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/*
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* Adds: PLPA
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* Adds all with Note *2: CAS, CAS2, MULS, MULU, CHK2, CMP2, DIVS, DIVU
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* All Fxxxx instructions are as per m68040 with exception to; FMOVEM NOTE3
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*
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* Does NOT implement MOVEP
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*
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* NOTES:
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* 2. Not applicable to the MC68EC040, MC68LC040, MC68EC060, and MC68LC060.
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* 3. These are software-supported instructions on the MC68040 and MC68060.
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*/
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static void m68060_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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static void m68060_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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{
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{
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M68kCPU *cpu = M68K_CPU(uc, obj);
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M68kCPU *cpu = M68K_CPU(uc, obj);
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@ -445,6 +445,15 @@ void m68k_switch_sp(CPUM68KState *env);
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void do_m68k_semihosting(CPUM68KState *env, int nr);
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void do_m68k_semihosting(CPUM68KState *env, int nr);
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/*
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/*
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* The 68000 family is defined in six main CPU classes, the 680[012346]0.
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* Generally each successive CPU adds enhanced data/stack/instructions.
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* However, some features are only common to one, or a few classes.
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* The features covers those subsets of instructons.
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*
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* CPU32/32+ are basically 680010 compatible with some 68020 class instructons,
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* and some additional CPU32 instructions. Mostly Supervisor state differences.
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*
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* The ColdFire core ISA is a RISC-style reduction of the 68000 series cpu.
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* There are 4 ColdFire core ISA revisions: A, A+, B and C.
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* There are 4 ColdFire core ISA revisions: A, A+, B and C.
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* Each feature covers the subset of instructions common to the
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* Each feature covers the subset of instructions common to the
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* ISA revisions mentioned.
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* ISA revisions mentioned.
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