yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-02-02 02:11:09 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/riscv: Disable guest FP support based on virtual status

Browse source 
When the Hypervisor extension is in use we only enable floating point
support when both status and vsstatus have enabled floating point
support.

Backports commit 29409c1d921d607873268671bf11a088efb5558e from qemu
This commit is contained in:
Alistair Francis 2020-03-22 01:49:03 -04:00 committed by Lioncash
parent 0d488f3a76
commit 347ad87e98
5 changed files with 17 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
qemu/header_gen.py
View file

@ -5566,6 +5566,7 @@ riscv_symbols = (
'riscv_cpu_do_unaligned_access',
'riscv_cpu_exec_interrupt',
'riscv_cpu_force_hs_excep_enabled',
'riscv_cpu_fp_enabled',
'riscv_cpu_get_fflags',
'riscv_cpu_get_phys_page_debug',
'riscv_cpu_list',

1
qemu/riscv32.h
View file

@ -3453,6 +3453,7 @@
#define riscv_cpu_do_unaligned_access riscv_cpu_do_unaligned_access_riscv32
#define riscv_cpu_exec_interrupt riscv_cpu_exec_interrupt_riscv32
#define riscv_cpu_force_hs_excep_enabled riscv_cpu_force_hs_excep_enabled_riscv32
#define riscv_cpu_fp_enabled riscv_cpu_fp_enabled_riscv32
#define riscv_cpu_get_fflags riscv_cpu_get_fflags_riscv32
#define riscv_cpu_get_phys_page_debug riscv_cpu_get_phys_page_debug_riscv32
#define riscv_cpu_list riscv_cpu_list_riscv32

1
qemu/riscv64.h
View file

@ -3453,6 +3453,7 @@
#define riscv_cpu_do_unaligned_access riscv_cpu_do_unaligned_access_riscv64
#define riscv_cpu_exec_interrupt riscv_cpu_exec_interrupt_riscv64
#define riscv_cpu_force_hs_excep_enabled riscv_cpu_force_hs_excep_enabled_riscv64
#define riscv_cpu_fp_enabled riscv_cpu_fp_enabled_riscv64
#define riscv_cpu_get_fflags riscv_cpu_get_fflags_riscv64
#define riscv_cpu_get_phys_page_debug riscv_cpu_get_phys_page_debug_riscv64
#define riscv_cpu_list riscv_cpu_list_riscv64

1
qemu/target/riscv/cpu.h
View file

@ -284,6 +284,7 @@ void riscv_cpu_do_interrupt(CPUState *cpu);
int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);

13
qemu/target/riscv/cpu_helper.c
View file

@ -95,6 +95,19 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
#if !defined(CONFIG_USER_ONLY)
/* Return true is floating point support is currently enabled */
bool riscv_cpu_fp_enabled(CPURISCVState *env)
{
if (env->mstatus & MSTATUS_FS) {
if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) {
return false;
}
return true;
}
return false;
}
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
{
target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |