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Backport the VBAR feature flag

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Backports commit 91db4642f868cf2e591b62d31a19d35b02ea791e from qemu to unicorn
This commit is contained in:
Lioncash 2018-02-02 08:23:47 -05:00
parent 291b5753eb
commit 35100ce4e0
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GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 20 additions and 3 deletions
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9
qemu/target-arm/cpu.c
View file

@ -348,6 +348,11 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
} else {
set_feature(env, ARM_FEATURE_V6);
}
/* Always define VBAR for V7 CPUs even if it doesn't exist in
* non-EL3 configs. This is needed by some legacy boards.
*/
set_feature(env, ARM_FEATURE_VBAR);
}
if (arm_feature(env, ARM_FEATURE_V6K)) {
set_feature(env, ARM_FEATURE_V6);
@ -391,6 +396,10 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
cpu->reset_sctlr |= (1 << 13);
}
if (arm_feature(env, ARM_FEATURE_EL3)) {
set_feature(env, ARM_FEATURE_VBAR);
}
register_cp_regs_for_features(cpu);
arm_cpu_register_gdb_regs_for_features(cpu);

1
qemu/target-arm/cpu.h
View file

@ -750,6 +750,7 @@ enum arm_features {
ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */
ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */
ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
ARM_FEATURE_VBAR, /* has cp15 VBAR */
ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */
};

13
qemu/target-arm/helper.c
View file

@ -751,9 +751,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
{ "PMINTENCLR", 15,9,14, 0,0,2, 0,
ARM_CP_NO_MIGRATE, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten),
NULL, NULL, pmintenclr_write, },
{ "VBAR", 0,12,0, 3,0,0, ARM_CP_STATE_BOTH,
0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.vbar_el[1]),
NULL, NULL, vbar_write, },
{ "SCR", 15,1,1, 0,0,0, 0,
0, PL1_RW, NULL, 0, offsetoflow32(CPUARMState, cp15.scr_el3),
NULL, NULL, scr_write },
@ -2708,6 +2705,16 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
}
if (arm_feature(env, ARM_FEATURE_VBAR)) {
ARMCPRegInfo vbar_cp_reginfo[] = {
{ "VBAR", 0,12,0, 3,0,0, ARM_CP_STATE_BOTH,
0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.vbar_el[1]),
NULL, NULL, vbar_write, },
REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, vbar_cp_reginfo);
}
/* Generic registers whose values depend on the implementation */
{
ARMCPRegInfo sctlr = {