yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-07-07 19:50:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: Implement data cache set allocation tags

Browse source 
This is DC GVA and DC GZVA, and the tag check for DC ZVA.

Backports commit eb821168db798302bd124a3b000cebc23bd0a395 from qemu
This commit is contained in:
Richard Henderson 2021-02-25 22:40:07 -05:00 committed by Lioncash
parent 33f5bdabb1
commit 35d0443056
3 changed files with 58 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
qemu/target/arm/cpu.h
View file

@ -2246,7 +2246,9 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400)
#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA #define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600)
#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700)
#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA
#define ARM_CP_FPU 0x1000 #define ARM_CP_FPU 0x1000
#define ARM_CP_SVE 0x2000 #define ARM_CP_SVE 0x2000
#define ARM_CP_NO_GDB 0x4000 #define ARM_CP_NO_GDB 0x4000

16
qemu/target/arm/helper.c
View file

@ -6700,6 +6700,22 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5,
.type = ARM_CP_NOP, .access = PL0_W, .type = ARM_CP_NOP, .access = PL0_W,
.accessfn = aa64_cacheop_poc_access }, .accessfn = aa64_cacheop_poc_access },
{ .name = "DC_GVA", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3,
.access = PL0_W, .type = ARM_CP_DC_GVA,
#ifndef CONFIG_USER_ONLY
/* Avoid overhead of an access check that always passes in user-mode */
.accessfn = aa64_zva_access,
#endif
},
{ .name = "DC_GZVA", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 4,
.access = PL0_W, .type = ARM_CP_DC_GZVA,
#ifndef CONFIG_USER_ONLY
/* Avoid overhead of an access check that always passes in user-mode */
.accessfn = aa64_zva_access,
#endif
},
REGINFO_SENTINEL REGINFO_SENTINEL
}; };

39
qemu/target/arm/translate-a64.c
View file

@ -2063,6 +2063,45 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
} }
gen_helper_dc_zva(tcg_ctx, tcg_ctx->cpu_env, tcg_rt); gen_helper_dc_zva(tcg_ctx, tcg_ctx->cpu_env, tcg_rt);
return; return;
case ARM_CP_DC_GVA:
{
TCGv_i64 clean_addr, tag;
/*
* DC_GVA, like DC_ZVA, requires that we supply the original
* pointer for an invalid page. Probe that address first.
*/
tcg_rt = cpu_reg(s, rt);
clean_addr = clean_data_tbi(s, tcg_rt);
gen_probe_access(s, clean_addr, MMU_DATA_STORE, MO_8);
if (s->ata) {
/* Extract the tag from the register to match STZGM. */
tag = tcg_temp_new_i64(tcg_ctx);
tcg_gen_shri_i64(tcg_ctx, tag, tcg_rt, 56);
gen_helper_stzgm_tags(tcg_ctx, tcg_ctx->cpu_env, clean_addr, tag);
tcg_temp_free_i64(tcg_ctx, tag);
}
}
return;
case ARM_CP_DC_GZVA:
{
TCGv_i64 clean_addr, tag;
/* For DC_GZVA, we can rely on DC_ZVA for the proper fault. */
tcg_rt = cpu_reg(s, rt);
clean_addr = clean_data_tbi(s, tcg_rt);
gen_helper_dc_zva(tcg_ctx, tcg_ctx->cpu_env, clean_addr);
if (s->ata) {
/* Extract the tag from the register to match STZGM. */
tag = tcg_temp_new_i64(tcg_ctx);
tcg_gen_shri_i64(tcg_ctx, tag, tcg_rt, 56);
gen_helper_stzgm_tags(tcg_ctx, tcg_ctx->cpu_env, clean_addr, tag);
tcg_temp_free_i64(tcg_ctx, tag);
}
}
return;
default: default:
break; break;
} }