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target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry

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On 32-bit exception entry, CPSR.J must always be set to 0
(see v7A Arm ARM DDI0406C.c B1.8.5). CPSR.IL must also
be cleared on 32-bit exception entry (see v8A Arm ARM
DDI0487C.a G1.10).

Clear these bits. (This fixes a bug which will never be noticed
by non-buggy guests.)

Backports commit 829f9fd394ab082753308cbda165c13eaf8fae49 from qemu
This commit is contained in:
Peter Maydell 2018-08-25 04:28:18 -04:00 committed by Lioncash
parent 16477f908e
commit 3619f707a6
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 0 deletions
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2
qemu/target/arm/helper.c
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@ -7252,6 +7252,8 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) {
env->uncached_cpsr |= CPSR_E; env->uncached_cpsr |= CPSR_E;
} }
/* J and IL must always be cleared for exception entry */
env->uncached_cpsr &= ~(CPSR_IL | CPSR_J);
env->daif |= mask; env->daif |= mask;
if (new_mode == ARM_CPU_MODE_HYP) { if (new_mode == ARM_CPU_MODE_HYP) {