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Fix arm & arm64 memleaks

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This commit is contained in:
danghvu 2016-01-31 16:22:20 -06:00
parent 7c9f851e72
commit 36e53ad8a1
5 changed files with 39 additions and 2 deletions
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2
qemu/hw/arm/tosa.c
View file

@ -20,7 +20,7 @@
static int tosa_init(struct uc_struct *uc, MachineState *machine) static int tosa_init(struct uc_struct *uc, MachineState *machine)
{ {
//cpu_arm_init(uc, "pxa255"); //cpu_arm_init(uc, "pxa255");
cpu_arm_init(uc, "cortex-a15"); // FIXME uc->cpu = cpu_arm_init(uc, "cortex-a15"); // FIXME
return 0; return 0;
} }

2
qemu/hw/arm/virt.c
View file

@ -54,7 +54,7 @@ static int machvirt_init(struct uc_struct *uc, MachineState *machine)
return -1; return -1;
} }
cpuobj = object_new(uc, object_class_get_name(oc)); uc->cpu = cpuobj = object_new(uc, object_class_get_name(oc));
object_property_set_bool(uc, cpuobj, true, "realized", NULL); object_property_set_bool(uc, cpuobj, true, "realized", NULL);
} }

18
qemu/target-arm/unicorn_aarch64.c
View file

@ -25,6 +25,23 @@ static void arm64_set_pc(struct uc_struct *uc, uint64_t address)
((CPUARMState *)uc->current_cpu->env_ptr)->pc = address; ((CPUARMState *)uc->current_cpu->env_ptr)->pc = address;
} }
void arm64_release(void* ctx);
void arm64_release(void* ctx)
{
TCGContext *s = (TCGContext *) ctx;
g_free(s->tb_ctx.tbs);
struct uc_struct* uc = s->uc;
ARMCPU* cpu = (ARMCPU*) uc->cpu;
g_free(cpu->cpreg_indexes);
g_free(cpu->cpreg_values);
g_free(cpu->cpreg_vmstate_indexes);
g_free(cpu->cpreg_vmstate_values);
release_common(ctx);
}
void arm64_reg_reset(struct uc_struct *uc) void arm64_reg_reset(struct uc_struct *uc)
{ {
CPUArchState *env = first_cpu->env_ptr; CPUArchState *env = first_cpu->env_ptr;
@ -103,5 +120,6 @@ void arm64_uc_init(struct uc_struct* uc)
uc->reg_write = arm64_reg_write; uc->reg_write = arm64_reg_write;
uc->reg_reset = arm64_reg_reset; uc->reg_reset = arm64_reg_reset;
uc->set_pc = arm64_set_pc; uc->set_pc = arm64_set_pc;
uc->release = arm64_release;
uc_common_init(uc); uc_common_init(uc);
} }

18
qemu/target-arm/unicorn_arm.c
View file

@ -25,6 +25,23 @@ static void arm_set_pc(struct uc_struct *uc, uint64_t address)
((CPUARMState *)uc->current_cpu->env_ptr)->regs[15] = address; ((CPUARMState *)uc->current_cpu->env_ptr)->regs[15] = address;
} }
void arm_release(void* ctx);
void arm_release(void* ctx)
{
TCGContext *s = (TCGContext *) ctx;
g_free(s->tb_ctx.tbs);
struct uc_struct* uc = s->uc;
ARMCPU* cpu = (ARMCPU*) uc->cpu;
g_free(cpu->cpreg_indexes);
g_free(cpu->cpreg_values);
g_free(cpu->cpreg_vmstate_indexes);
g_free(cpu->cpreg_vmstate_values);
release_common(ctx);
}
void arm_reg_reset(struct uc_struct *uc) void arm_reg_reset(struct uc_struct *uc)
{ {
(void)uc; (void)uc;
@ -134,5 +151,6 @@ void arm_uc_init(struct uc_struct* uc)
uc->reg_reset = arm_reg_reset; uc->reg_reset = arm_reg_reset;
uc->set_pc = arm_set_pc; uc->set_pc = arm_set_pc;
uc->stop_interrupt = arm_stop_interrupt; uc->stop_interrupt = arm_stop_interrupt;
uc->release = arm_release;
uc_common_init(uc); uc_common_init(uc);
} }

1
qemu/unicorn_common.h
View file

@ -42,6 +42,7 @@ static void release_common(void *t)
g_free(def->args_ct); g_free(def->args_ct);
g_free(def->sorted_args); g_free(def->sorted_args);
g_free(s->tcg_op_defs); g_free(s->tcg_op_defs);
TCGPool *po, *to; TCGPool *po, *to;
for (po = s->pool_first; po; po = to) { for (po = s->pool_first; po; po = to) {
to = po->next; to = po->next;