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target/arm: Implement SVE Integer Arithmetic - Unpredicated Group

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Backports commit fea98f9c3077e4666f6d4933030b5891fbd6bb12 from qemu
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Richard Henderson 2018-05-20 04:36:49 -04:00 committed by Lioncash
parent 1730d3cff0
commit 390bd68287
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2 changed files with 47 additions and 0 deletions
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13
qemu/target/arm/sve.decode
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@ -66,6 +66,9 @@
# Three predicate operand, with governing predicate, flag setting # Three predicate operand, with governing predicate, flag setting
@pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s
# Three operand, vector element size
@rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz
# Two register operand, with governing predicate, vector element size # Two register operand, with governing predicate, vector element size
@rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \ @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
&rprr_esz rn=%reg_movprfx &rprr_esz rn=%reg_movprfx
@ -203,6 +206,16 @@ MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm
MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD
MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB
### SVE Integer Arithmetic - Unpredicated Group
# SVE integer add/subtract vectors (unpredicated)
ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm
SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm
SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm
UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm
SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm
UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm
### SVE Logical - Unpredicated Group ### SVE Logical - Unpredicated Group
# SVE bitwise logical operations (unpredicated) # SVE bitwise logical operations (unpredicated)

34
qemu/target/arm/translate-sve.c
View file

@ -256,6 +256,40 @@ static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm); return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm);
} }
/*
*** SVE Integer Arithmetic - Unpredicated Group
*/
static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
{
return do_vector3_z(s, tcg_gen_gvec_add, a->esz, a->rd, a->rn, a->rm);
}
static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
{
return do_vector3_z(s, tcg_gen_gvec_sub, a->esz, a->rd, a->rn, a->rm);
}
static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
{
return do_vector3_z(s, tcg_gen_gvec_ssadd, a->esz, a->rd, a->rn, a->rm);
}
static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
{
return do_vector3_z(s, tcg_gen_gvec_sssub, a->esz, a->rd, a->rn, a->rm);
}
static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
{
return do_vector3_z(s, tcg_gen_gvec_usadd, a->esz, a->rd, a->rn, a->rm);
}
static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
{
return do_vector3_z(s, tcg_gen_gvec_ussub, a->esz, a->rd, a->rn, a->rm);
}
/* /*
*** SVE Integer Arithmetic - Binary Predicated Group *** SVE Integer Arithmetic - Binary Predicated Group
*/ */